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gpu: nvgpu: print length of various ctxsw'ed register lists

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Add function nvgpu_netlist_print_ctxsw_reg_info to print the number of entries
present in each of the ctxsw'ed register lists.

Parse and populate GRCTX_REG_LIST_PERF_SYS_CONTROL register entires.

Jira NVGPU-6096

Change-Id: I7ea25c397a29793ede4eb0c408a5150a66de9e18
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2406379
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Antony Clince Alex
2020-08-31 13:18:30 +05:30
committed by Alex Waterman
parent e367f670fd
commit 58f58d0097
3 changed files with 89 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
drivers/gpu/nvgpu/common/netlist/netlist.c
View File

@@ -610,7 +610,6 @@ int nvgpu_netlist_init_ctx_vars(struct gk20a *g)
if (err != 0) {
nvgpu_err(g, "nvgpu_init_sim_netlist_ctx_vars failed!");
}
return err;
} else
#endif
{
@@ -618,8 +617,12 @@ int nvgpu_netlist_init_ctx_vars(struct gk20a *g)
if (err != 0) {
nvgpu_err(g, "nvgpu_netlist_init_ctx_vars_fw failed!");
}
return err;
}
#ifdef CONFIG_NVGPU_DEBUGGER
nvgpu_netlist_print_ctxsw_reg_info(g);
#endif
return err;
}
void nvgpu_netlist_deinit_ctx_vars(struct gk20a *g)
@@ -944,6 +947,67 @@ u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g)
#endif
return count;
}
void nvgpu_netlist_print_ctxsw_reg_info(struct gk20a *g)
{
nvgpu_log_info(g, "<<<<---------- CTXSW'ed register info ---------->>>>");
nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_COUNT :%d",
nvgpu_netlist_get_sys_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_COUNT :%d",
nvgpu_netlist_get_gpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_COUNT :%d",
nvgpu_netlist_get_tpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT :%d",
nvgpu_netlist_get_zcull_gpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_SYS_COUNT :%d",
nvgpu_netlist_get_pm_sys_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_GPC_COUNT :%d",
nvgpu_netlist_get_pm_gpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_TPC_COUNT :%d",
nvgpu_netlist_get_pm_tpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_COUNT :%d",
nvgpu_netlist_get_ppc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_COUNT :%d",
nvgpu_netlist_get_etpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_PPC_COUNT :%d",
nvgpu_netlist_get_pm_ppc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_SYS_COUNT :%d",
nvgpu_netlist_get_perf_sys_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_SYSROUTER_COUNT :%d",
nvgpu_netlist_get_perf_sys_router_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_SYS_CONTROL_COUNT :%d",
nvgpu_netlist_get_perf_sys_control_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_PMA_COUNT :%d",
nvgpu_netlist_get_perf_pma_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_FBP_COUNT :%d",
nvgpu_netlist_get_fbp_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_FBPROUTER_COUNT :%d",
nvgpu_netlist_get_fbp_router_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_GPC_COUNT :%d",
nvgpu_netlist_get_perf_gpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_GPCROUTER_COUNT :%d",
nvgpu_netlist_get_gpc_router_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_LTC_COUNT :%d",
nvgpu_netlist_get_pm_ltc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_ROP_COUNT :%d",
nvgpu_netlist_get_pm_rop_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_UNICAST_GPC_COUNT :%d",
nvgpu_netlist_get_pm_ucgpc_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_CAU_COUNT :%d",
nvgpu_netlist_get_pm_cau_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PM_FBPA_COUNT :%d",
nvgpu_netlist_get_pm_fbpa_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_FBP_CONTROL_COUNT :%d",
nvgpu_netlist_get_perf_fbp_control_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_GPC_CONTROL_COUNT :%d",
nvgpu_netlist_get_perf_gpc_control_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PERF_PMA_CONTROL_COUNT :%d",
nvgpu_netlist_get_perf_pma_control_ctxsw_regs(g)->count);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
nvgpu_next_netlist_print_ctxsw_reg_info(g);
#endif
}
#endif /* CONFIG_NVGPU_DEBUGGER */
#ifdef CONFIG_NVGPU_NON_FUSA

22
drivers/gpu/nvgpu/common/sim/sim_netlist.c
View File

@@ -55,6 +55,7 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g)
struct netlist_aiv_list *pm_ppc_ctxsw_regs;
struct netlist_aiv_list *perf_sys_ctxsw_regs;
struct netlist_aiv_list *perf_sysrouter_ctxsw_regs;
struct netlist_aiv_list *perf_sys_control_ctxsw_regs;
struct netlist_aiv_list *perf_pma_ctxsw_regs;
struct netlist_aiv_list *perf_fbp_ctxsw_regs;
struct netlist_aiv_list *perf_fbprouter_ctxsw_regs;
@@ -108,6 +109,8 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g)
perf_sys_ctxsw_regs = nvgpu_netlist_get_perf_sys_ctxsw_regs(g);
perf_sysrouter_ctxsw_regs =
nvgpu_netlist_get_perf_sys_router_ctxsw_regs(g);
perf_sys_control_ctxsw_regs =
nvgpu_netlist_get_perf_sys_control_ctxsw_regs(g);
perf_pma_ctxsw_regs = nvgpu_netlist_get_perf_pma_ctxsw_regs(g);
perf_fbp_ctxsw_regs = nvgpu_netlist_get_fbp_ctxsw_regs(g);
perf_fbprouter_ctxsw_regs =
@@ -189,6 +192,8 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g)
&perf_sys_ctxsw_regs->count);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PERF_SYSROUTER_COUNT", 0,
&perf_sysrouter_ctxsw_regs->count);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PERF_SYS_CONTROL_COUNT", 0,
&perf_sys_control_ctxsw_regs->count);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PERF_PMA_COUNT", 0,
&perf_pma_ctxsw_regs->count);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PERF_FBP_COUNT", 0,
@@ -288,6 +293,9 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g)
== NULL) {
goto fail;
}
if (nvgpu_netlist_alloc_aiv_list(g, perf_sys_control_ctxsw_regs) == NULL) {
goto fail;
}
if (nvgpu_netlist_alloc_aiv_list(g, perf_pma_ctxsw_regs) == NULL) {
goto fail;
}
@@ -554,6 +562,20 @@ int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g)
l[i].addr, l[i].index, l[i].value);
}
nvgpu_log(g, gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_PERF_SYS_CONTROL");
for (i = 0; i < perf_sys_control_ctxsw_regs->count; i++) {
struct netlist_aiv *l = perf_sys_control_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PERF_SYS_CONTROL:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PERF_SYS_CONTROL:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PERF_SYS_CONTROL:VALUE",
i, &l[i].value);
nvgpu_log(g, gpu_dbg_info | gpu_dbg_fn,
"addr:0x%#08x index:0x%08x value:0x%08x",
l[i].addr, l[i].index, l[i].value);
}
nvgpu_log(g, gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_PERF_PMA");
for (i = 0; i < perf_pma_ctxsw_regs->count; i++) {
struct netlist_aiv *l = perf_pma_ctxsw_regs->l;

1
drivers/gpu/nvgpu/include/nvgpu/netlist.h
View File

@@ -392,6 +392,7 @@ u32 nvgpu_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g);
void nvgpu_netlist_print_ctxsw_reg_info(struct gk20a *g);
#endif /* CONFIG_NVGPU_DEBUGGER */
#ifdef CONFIG_NVGPU_NON_FUSA