gpu: nvgpu: add CONFIG_NVGPU_TEGRA_FUSE

Encapsulate the tegra fuse functionality under the config flag
CONFIG_NVGPU_TEGRA_FUSE.

Bug 2834141

Change-Id: I54c9e82360e8a24008ea14eb55af80f81d325cdc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306432
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/include/nvgpu/fuse.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,10 +30,14 @@
 struct gk20a;
 
 #include <nvgpu/types.h>
+#include <nvgpu/errno.h>
+
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
 
 #ifdef CONFIG_NVGPU_NON_FUSA
-int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g);
-#endif
+int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id);
+int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
+#endif /* CONFIG_NVGPU_NON_FUSA */
 
 /**
  * @brief -  Write Fuse bypass register which controls fuse bypass.
@@ -97,7 +101,50 @@ void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val);
  */
 int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val);
 
+#else /* CONFIG_NVGPU_TEGRA_FUSE */
+
 #ifdef CONFIG_NVGPU_NON_FUSA
-int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val);
-#endif
+static inline int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id)
+{
+	return -EINVAL;
+}
+
+static inline int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g,
+						       u32 *val)
+{
+	return -EINVAL;
+}
+#endif /* CONFIG_NVGPU_NON_FUSA */
+
+static inline void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
+{
+}
+
+static inline void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
+{
+}
+
+static inline void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g,
+							       u32 val)
+{
+}
+
+static inline void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g,
+							       u32 val)
+{
+}
+
+static inline int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g,
+							   u32 *val)
+{
+	/*
+	 * Setting gcplex_config fuse to wpr_enabled/vpr_auto_fetch_disable
+	 * by default that is expected on the production chip.
+	 */
+	*val = 0x4;
+
+	return 0;
+}
+
+#endif /* CONFIG_NVGPU_TEGRA_FUSE */
 #endif /* NVGPU_FUSE_H */

drivers/gpu/nvgpu/include/nvgpu/gops_gr.h

@@ -1065,7 +1065,9 @@ struct gops_gr {
 	void (*get_ovr_perf_regs)(struct gk20a *g,
 				  u32 *num_ovr_perf_regs,
 				  u32 **ovr_perf_regsr);
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
 	void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
+#endif
 	int (*decode_egpc_addr)(struct gk20a *g,
 				u32 addr, enum ctxsw_addr_type *addr_type,
 				u32 *gpc_num, u32 *tpc_num,

drivers/gpu/nvgpu/include/nvgpu/soc.h

@@ -26,6 +26,7 @@
 
 struct gk20a;
 
+#ifdef CONFIG_NVGPU_TEGRA_FUSE
 /**
  * @brief Check whether running on silicon or not.
  *
@@ -114,4 +115,42 @@ bool nvgpu_is_soc_t194_a01(struct gk20a *g);
  */
 int nvgpu_init_soc_vars(struct gk20a *g);
 
+#else /* CONFIG_NVGPU_TEGRA_FUSE */
+
+static inline bool nvgpu_platform_is_silicon(struct gk20a *g)
+{
+	return true;
+}
+
+static inline bool nvgpu_platform_is_simulation(struct gk20a *g)
+{
+	return false;
+}
+
+static inline bool nvgpu_platform_is_fpga(struct gk20a *g)
+{
+	return false;
+}
+
+static inline bool nvgpu_is_hypervisor_mode(struct gk20a *g)
+{
+	return false;
+}
+
+static inline bool nvgpu_is_bpmp_running(struct gk20a *g)
+{
+	return false;
+}
+
+static inline bool nvgpu_is_soc_t194_a01(struct gk20a *g)
+{
+	return false;
+}
+
+static inline int nvgpu_init_soc_vars(struct gk20a *g)
+{
+	return 0;
+}
+#endif /* CONFIG_NVGPU_TEGRA_FUSE */
+
 #endif /* NVGPU_SOC_H */