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gpu: nvgpu: Remove mm.get_iova_addr

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Volta changes for equivalent change on nvgpu.

JIRA NVGPU-30

Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530863
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2017-06-08 15:05:19 -07:00
committed by mobile promotions
parent 3e3c192040
commit 5a5792d911
3 changed files with 8 additions and 6 deletions
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4
drivers/gpu/nvgpu/gv11b/fb_gv11b.c
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@@ -101,8 +101,8 @@ static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
else else
compbit_store_iova = g->ops.mm.get_iova_addr(g, compbit_store_iova = nvgpu_mem_get_addr(g,
gr->compbit_store.mem.priv.sgt->sgl, 0); &gr->compbit_store.mem);
compbit_base_post_divide64 = compbit_store_iova >> compbit_base_post_divide64 = compbit_store_iova >>
fb_mmu_cbc_base_address_alignment_shift_v(); fb_mmu_cbc_base_address_alignment_shift_v();

5
drivers/gpu/nvgpu/gv11b/mm_gv11b.c
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@@ -260,10 +260,10 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate)
* checking bit 36 of the phsyical address. So if a mapping should allocte lines * checking bit 36 of the phsyical address. So if a mapping should allocte lines
* in the L3 this bit must be set. * in the L3 this bit must be set.
*/ */
u64 gv11b_gpu_phys_addr(struct gk20a *g, static u64 gv11b_gpu_phys_addr(struct gk20a *g,
struct nvgpu_gmmu_attrs *attrs, u64 phys) struct nvgpu_gmmu_attrs *attrs, u64 phys)
{ {
if (attrs->t19x_attrs.l3_alloc) if (attrs && attrs->t19x_attrs.l3_alloc)
return phys | NVGPU_L3_ALLOC_BIT; return phys | NVGPU_L3_ALLOC_BIT;
return phys; return phys;
@@ -322,6 +322,7 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g)
void gv11b_init_mm(struct gpu_ops *gops) void gv11b_init_mm(struct gpu_ops *gops)
{ {
gp10b_init_mm(gops); gp10b_init_mm(gops);
gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr;
gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported;
gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.init_inst_block = gv11b_init_inst_block;
gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending;

3
drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
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@@ -143,13 +143,14 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c,
struct nvgpu_mem *inst_block) struct nvgpu_mem *inst_block)
{ {
struct gk20a *g = c->g; struct gk20a *g = c->g;
struct vm_gk20a *vm = c->vm;
u32 lo, hi; u32 lo, hi;
u32 subctx_id = 0; u32 subctx_id = 0;
u32 format_word; u32 format_word;
u32 pdb_addr_lo, pdb_addr_hi; u32 pdb_addr_lo, pdb_addr_hi;
u64 pdb_addr; u64 pdb_addr;
pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem->priv.sgt->sgl, 0); pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem);
pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
pdb_addr_hi = u64_hi32(pdb_addr); pdb_addr_hi = u64_hi32(pdb_addr);
format_word = ram_in_sc_page_dir_base_target_f( format_word = ram_in_sc_page_dir_base_target_f(