From 5a9d4932bcd73b804ff71bbba86655c85f0d8171 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 23 Apr 2019 14:28:08 -0700 Subject: [PATCH] gpu: nvgpu: avoid including ram header in gr falcon Avoid including hw_ram_gm20b.h in gr_falcon_gm20b.c. Instead use ops for getting ramin base shift. JIRA NVGPU-3211 Change-Id: I679d78064600d42038d4f01a9d5c14a64998dcf0 Signed-off-by: Seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/2103714 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c index 7ee565df6..356e164e4 100644 --- a/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/falcon/gr_falcon_gm20b.c @@ -32,7 +32,6 @@ #include "common/gr/gr_priv.h" #include -#include #define GR_FECS_POLL_INTERVAL 5U /* usec */ @@ -951,7 +950,8 @@ u32 gm20b_gr_falcon_get_fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) { u64 ptr = nvgpu_inst_block_addr(g, inst_block) >> - ram_in_base_shift_v(); + g->ops.ramin.base_shift(); + u32 aperture = nvgpu_aperture_mask(g, inst_block, gr_fecs_current_ctx_target_sys_mem_ncoh_f(), gr_fecs_current_ctx_target_sys_mem_coh_f(),