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gpu: nvgpu: Fix CERT INT30-C errors in gr.intr unit

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Fix CERT INT30-c errors in gr.intr unit.

cert_violation: Unsigned integer operation may wrap.

Use nvgpu_safe_ops macros for addition

Jira NVGPU-3412

Change-Id: I49d08318fde54d4de36501b8ea2a413edd0f30ff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123051
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-05-21 11:42:17 -07:00
committed by mobile promotions
parent b60dca5e0a
commit 5ab6f3a593
2 changed files with 26 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
View File

@@ -376,9 +376,8 @@ void gm20b_gr_intr_get_trapped_method_info(struct gk20a *g,
u32 gm20b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset, u32 gm20b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
struct nvgpu_gr_tpc_exception *pending_tpc) struct nvgpu_gr_tpc_exception *pending_tpc)
{ {
u32 tpc_exception = nvgpu_readl(g, u32 tpc_exception = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_tpccs_tpc_exception_r() gr_gpc0_tpc0_tpccs_tpc_exception_r(), offset));
+ offset);
(void) memset(pending_tpc, 0, sizeof(struct nvgpu_gr_tpc_exception)); (void) memset(pending_tpc, 0, sizeof(struct nvgpu_gr_tpc_exception));

47
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
View File

@@ -418,14 +418,15 @@ int gp10b_gr_intr_handle_sm_exception(struct gk20a *g,
void gp10b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc) void gp10b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc)
{ {
u32 offset = nvgpu_gr_gpc_offset(g, gpc) + nvgpu_gr_tpc_offset(g, tpc); u32 offset = nvgpu_safe_add_u32(nvgpu_gr_gpc_offset(g, gpc),
nvgpu_gr_tpc_offset(g, tpc));
u32 esr; u32 esr;
u32 ecc_stats_reg_val; u32 ecc_stats_reg_val;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, " "); nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, " ");
esr = nvgpu_readl(g, esr = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); gr_gpc0_tpc0_tex_m_hww_esr_r(), offset));
nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr);
if ((esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) != 0U) { if ((esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) != 0U) {
@@ -433,30 +434,30 @@ void gp10b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc)
"Single bit error detected in TEX!"); "Single bit error detected in TEX!");
/* Pipe 0 counters */ /* Pipe 0 counters */
nvgpu_writel(g, nvgpu_writel(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, gr_pri_gpc0_tpc0_tex_m_routing_r(), offset),
gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
ecc_stats_reg_val = nvgpu_readl(g, ecc_stats_reg_val = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(), offset));
g->ecc.gr.tex_ecc_total_sec_pipe0_count[gpc][tpc].counter += g->ecc.gr.tex_ecc_total_sec_pipe0_count[gpc][tpc].counter +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v( gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(
ecc_stats_reg_val); ecc_stats_reg_val);
ecc_stats_reg_val &= ecc_stats_reg_val &=
~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
nvgpu_writel(g, nvgpu_writel(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(), offset),
ecc_stats_reg_val); ecc_stats_reg_val);
ecc_stats_reg_val = nvgpu_readl(g, ecc_stats_reg_val = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(), offset));
g->ecc.gr.tex_unique_ecc_sec_pipe0_count[gpc][tpc].counter += g->ecc.gr.tex_unique_ecc_sec_pipe0_count[gpc][tpc].counter +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v( gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(
ecc_stats_reg_val); ecc_stats_reg_val);
ecc_stats_reg_val &= ecc_stats_reg_val &=
~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
nvgpu_writel(g, nvgpu_writel(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(), offset),
ecc_stats_reg_val); ecc_stats_reg_val);
@@ -526,23 +527,23 @@ void gp10b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc)
/* Pipe 1 counters */ /* Pipe 1 counters */
nvgpu_writel(g, nvgpu_writel(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, gr_pri_gpc0_tpc0_tex_m_routing_r(), offset),
gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
ecc_stats_reg_val = nvgpu_readl(g, ecc_stats_reg_val = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(), offset));
g->ecc.gr.tex_ecc_total_ded_pipe1_count[gpc][tpc].counter += g->ecc.gr.tex_ecc_total_ded_pipe1_count[gpc][tpc].counter +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v( gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(
ecc_stats_reg_val); ecc_stats_reg_val);
ecc_stats_reg_val &= ecc_stats_reg_val &=
~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
nvgpu_writel(g, nvgpu_writel(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(), offset),
ecc_stats_reg_val); ecc_stats_reg_val);
ecc_stats_reg_val = nvgpu_readl(g, ecc_stats_reg_val = nvgpu_readl(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(), offset));
g->ecc.gr.tex_unique_ecc_ded_pipe1_count[gpc][tpc].counter += g->ecc.gr.tex_unique_ecc_ded_pipe1_count[gpc][tpc].counter +=
gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v( gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(
ecc_stats_reg_val); ecc_stats_reg_val);
@@ -554,8 +555,8 @@ void gp10b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc)
ecc_stats_reg_val); ecc_stats_reg_val);
nvgpu_writel(g, nvgpu_writel(g, nvgpu_safe_add_u32(
gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, gr_pri_gpc0_tpc0_tex_m_routing_r(), offset),
gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
} }