From 5ad253cee707b8291df14e171f70af0cf738ddb2 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Thu, 8 Nov 2018 22:57:02 -0500 Subject: [PATCH] gpu: nvgpu: clk: use consistent type for regime id The clk module was using u8's and u32's for the regime ID. Since the regime id is only a byte, just use u8's. This eliminates MISRA rule 10.3 violations for implicit assignments to different types. JIRA NVGPU-1008 Change-Id: Id3d1394402b248818cf959b46cd48611755f6912 Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1946259 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk.c | 6 +++--- drivers/gpu/nvgpu/clk/clk.h | 12 ++++++------ drivers/gpu/nvgpu/include/nvgpu/pmuif/ctrlclkavfs.h | 6 +++--- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 457b4d6eb..d1b56de36 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c @@ -507,7 +507,7 @@ done: return status; } -static u32 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz) +static u8 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz) { struct fll_device *pflldev; u8 j; @@ -527,7 +527,7 @@ static u32 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz) return CTRL_CLK_FLL_REGIME_ID_INVALID; } -static int set_regime_id(struct gk20a *g, u32 domain, u32 regimeid) +static int set_regime_id(struct gk20a *g, u32 domain, u8 regimeid) { struct fll_device *pflldev; u8 j; @@ -543,7 +543,7 @@ static int set_regime_id(struct gk20a *g, u32 domain, u32 regimeid) return -EINVAL; } -static int get_regime_id(struct gk20a *g, u32 domain, u32 *regimeid) +static int get_regime_id(struct gk20a *g, u32 domain, u8 *regimeid) { struct fll_device *pflldev; u8 j; diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h index 71b1de6c6..16f3b7ea0 100644 --- a/drivers/gpu/nvgpu/clk/clk.h +++ b/drivers/gpu/nvgpu/clk/clk.h @@ -68,14 +68,14 @@ struct change_fll_clk { struct set_fll_clk { u32 voltuv; u16 gpc2clkmhz; - u32 current_regime_id_gpc; - u32 target_regime_id_gpc; + u8 current_regime_id_gpc; + u8 target_regime_id_gpc; u16 sys2clkmhz; - u32 current_regime_id_sys; - u32 target_regime_id_sys; + u8 current_regime_id_sys; + u8 target_regime_id_sys; u16 xbar2clkmhz; - u32 current_regime_id_xbar; - u32 target_regime_id_xbar; + u8 current_regime_id_xbar; + u8 target_regime_id_xbar; }; #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS 9U diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/ctrlclkavfs.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/ctrlclkavfs.h index fe67e7c40..44dd75b02 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/ctrlclkavfs.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/ctrlclkavfs.h @@ -59,9 +59,9 @@ #define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000U) #define CTRL_CLK_FLL_TYPE_DISABLED 0U -#define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000U) -#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001U) -#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002U) +#define CTRL_CLK_FLL_REGIME_ID_INVALID ((u8)0x00000000) +#define CTRL_CLK_FLL_REGIME_ID_FFR ((u8)0x00000001) +#define CTRL_CLK_FLL_REGIME_ID_FR ((u8)0x00000002) #define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000U) #define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001U)