diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c
index 11f972b86..8e2e555c7 100644
--- a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c
+++ b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c
@@ -51,6 +51,7 @@ void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu)
 	nvgpu_err(g, "pmu state: %d", pmu->pmu_state);
 	nvgpu_err(g, "elpg state: %d", pmu->elpg_stat);
 
-	/* PMU may crash due to FECS crash. Dump FECS status */
+	/* PMU may crash due to FECS crash. Dump FECS and GPCCS status */
 	gk20a_fecs_dump_falcon_stats(g);
+	gk20a_gpccs_dump_falcon_stats(g);
 }
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index aed130e41..77babc7b2 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1407,6 +1407,7 @@ static void gk20a_fifo_handle_chsw_fault(struct gk20a *g)
 	intr = gk20a_readl(g, fifo_intr_chsw_error_r());
 	nvgpu_err(g, "chsw: %08x", intr);
 	gk20a_fecs_dump_falcon_stats(g);
+	gk20a_gpccs_dump_falcon_stats(g);
 	gk20a_writel(g, fifo_intr_chsw_error_r(), intr);
 }
 
@@ -1723,6 +1724,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
 
 		if (ctxsw) {
 			gk20a_fecs_dump_falcon_stats(g);
+			gk20a_gpccs_dump_falcon_stats(g);
 			nvgpu_err(g, "gr_status_r : 0x%x",
 					gk20a_readl(g, gr_status_r()));
 		}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 5d1545c20..d042bd7b9 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -121,6 +121,83 @@ int gr_gk20a_get_ctx_id(struct gk20a *g,
 	return 0;
 }
 
+void gk20a_gpccs_dump_falcon_stats(struct gk20a *g)
+{
+	unsigned int i;
+
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqstat : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_irqstat_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmode : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmode_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqmask : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_irqmask_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_irqdest : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_irqdest_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_debug1 : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_debug1_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_debuginfo : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_debuginfo_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_engctl : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_engctl_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_curctx : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_curctx_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_falcon_nxtctx : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_falcon_nxtctx_r()));
+	nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_status_1 : %d",
+		gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r()));
+
+	for (i = 0; i < g->ops.gr.gpc0_gpccs_ctxsw_mailbox_size(); i++) {
+		nvgpu_err(g, "gr_gpc0_gpccs_ctxsw_mailbox_r(%d) : 0x%x",
+			i, gk20a_readl(g, gr_gpc0_gpccs_ctxsw_mailbox_r(i)));
+	}
+
+
+	gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
+		gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
+		gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_IMB));
+	nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_IMB : 0x%x",
+		gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
+
+	gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
+		gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
+		gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_DMB));
+	nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_DMB : 0x%x",
+		gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
+
+	gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
+		gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
+		gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CSW));
+	nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CSW : 0x%x",
+		gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
+
+	gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
+		gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
+		gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_CTX));
+	nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_CTX : 0x%x",
+		gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
+
+	gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
+		gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
+		gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_EXCI));
+	nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_EXCI : 0x%x",
+		gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
+
+
+	for (i = 0; i < 4U; i++) {
+		gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
+			gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
+			gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_PC));
+		nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_PC : 0x%x",
+			gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
+
+		gk20a_writel(g, gr_gpc0_gpccs_falcon_icd_cmd_r(),
+			gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f() |
+			gr_gpc0_gpccs_falcon_icd_cmd_idx_f(PMU_FALCON_REG_SP));
+		nvgpu_err(g, "GPC0_GPCCS_FALCON_REG_SP : 0x%x",
+			gk20a_readl(g, gr_gpc_gpccs_falcon_icd_rdata_r()));
+	}
+}
+
 void gk20a_fecs_dump_falcon_stats(struct gk20a *g)
 {
 	unsigned int i;
@@ -527,6 +604,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
 			   "timeout waiting on mailbox=%d value=0x%08x",
 			   mailbox_id, reg);
 		gk20a_fecs_dump_falcon_stats(g);
+		gk20a_gpccs_dump_falcon_stats(g);
 		gk20a_gr_debug_dump(g);
 		return -1;
 	} else if (check == WAIT_UCODE_ERROR) {
@@ -534,6 +612,7 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id,
 			   "ucode method failed on mailbox=%d value=0x%08x",
 			   mailbox_id, reg);
 		gk20a_fecs_dump_falcon_stats(g);
+		gk20a_gpccs_dump_falcon_stats(g);
 		return -1;
 	}
 
@@ -5297,9 +5376,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
 	} else if ((gr_fecs_intr &
 			gr_fecs_host_int_status_watchdog_active_f()) != 0U) {
 		/* currently, recovery is not initiated */
-		nvgpu_err(g, "fecs watchdog triggered for channel %u, "
-				"cannot ctxsw anymore !!", chid);
+		nvgpu_err(g, "fecs watchdog triggered for channel %u", chid);
 		gk20a_fecs_dump_falcon_stats(g);
+		gk20a_gpccs_dump_falcon_stats(g);
+		gk20a_gr_debug_dump(g);
 	} else if ((gr_fecs_intr &
 		gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) {
 		u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6));
@@ -5323,6 +5403,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
 			"unhandled fecs error interrupt 0x%08x for channel %u",
 			gr_fecs_intr, chid);
 		gk20a_fecs_dump_falcon_stats(g);
+		gk20a_gpccs_dump_falcon_stats(g);
 	}
 
 	gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 901835c81..2cd6a4f69 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -438,6 +438,7 @@ struct gr_gk20a {
 };
 
 void gk20a_fecs_dump_falcon_stats(struct gk20a *g);
+void gk20a_gpccs_dump_falcon_stats(struct gk20a *g);
 
 /* contexts associated with a TSG */
 struct nvgpu_gr_ctx {
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 31edf69f7..ffbe35e30 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -326,6 +326,7 @@ static const struct gpu_ops gm20b_ops = {
 			gr_gm20b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
 		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
+		.gpc0_gpccs_ctxsw_mailbox_size = gr_gpc0_gpccs_ctxsw_mailbox__size_1_v,
 		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.map_global_ctx_buffers = gr_gk20a_map_global_ctx_buffers,
 		.commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 17f3ccf57..22423a4b9 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -398,6 +398,7 @@ static const struct gpu_ops gp106_ops = {
 			gr_gm20b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
 		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
+		.gpc0_gpccs_ctxsw_mailbox_size = gr_gpc0_gpccs_ctxsw_mailbox__size_1_v,
 		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.map_global_ctx_buffers = gr_gk20a_map_global_ctx_buffers,
 		.commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index c6f3c3d92..048c56e19 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -361,6 +361,7 @@ static const struct gpu_ops gp10b_ops = {
 			gr_gm20b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
 		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
+		.gpc0_gpccs_ctxsw_mailbox_size = gr_gpc0_gpccs_ctxsw_mailbox__size_1_v,
 		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.map_global_ctx_buffers = gr_gk20a_map_global_ctx_buffers,
 		.commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 3982006e9..a763757e8 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -483,6 +483,7 @@ static const struct gpu_ops gv100_ops = {
 			gr_gv11b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
 		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
+		.gpc0_gpccs_ctxsw_mailbox_size = gr_gpc0_gpccs_ctxsw_mailbox__size_1_v,
 		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.map_global_ctx_buffers = gr_gk20a_map_global_ctx_buffers,
 		.commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 1449c082e..db5597243 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -445,6 +445,7 @@ static const struct gpu_ops gv11b_ops = {
 			gr_gv11b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
 		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
+		.gpc0_gpccs_ctxsw_mailbox_size = gr_gpc0_gpccs_ctxsw_mailbox__size_1_v,
 		.alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
 		.map_global_ctx_buffers = gr_gk20a_map_global_ctx_buffers,
 		.commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index f8bc921bc..19bfaee02 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -517,6 +517,7 @@ struct gpu_ops {
 					u32 *priv_addr_table,
 					u32 *priv_addr_table_index);
 		u32 (*fecs_ctxsw_mailbox_size)(void);
+		u32 (*gpc0_gpccs_ctxsw_mailbox_size)(void);
 		int (*init_sw_bundle64)(struct gk20a *g);
 		int (*alloc_global_ctx_buffers)(struct gk20a *g);
 		int (*map_global_ctx_buffers)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
index 826108f10..376cc8f96 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_gr_gk20a.h
@@ -1380,6 +1380,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
 	return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420U;
@@ -3804,4 +3808,61 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000U;
 }
+
+static inline u32 gr_gpc0_gpccs_falcon_irqstat_r(void)
+{
+	return 0x00502008U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqmode_r(void)
+{
+	return 0x0050200cU;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqmask_r(void)
+{
+	return 0x00502018U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_irqdest_r(void)
+{
+	return 0x0050201cU;
+}
+static inline u32 gr_gpc0_gpccs_falcon_debug1_r(void)
+{
+	return 0x00502090U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_debuginfo_r(void)
+{
+	return 0x00502094U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_engctl_r(void)
+{
+	return 0x005020a4U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_curctx_r(void)
+{
+	return 0x00502050U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_nxtctx_r(void)
+{
+	return 0x00502054U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox_r(u32 i)
+{
+	return 0x00502800U + i*4U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_r(void)
+{
+	return 0x00502200U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_opc_rreg_f(void)
+{
+	return 0x8U;
+}
+static inline u32 gr_gpc0_gpccs_falcon_icd_cmd_idx_f(u32 v)
+{
+	return (v & 0x1fU) << 8U;
+}
+static inline u32 gr_gpc_gpccs_falcon_icd_rdata_r(void)
+{
+	return 0x0050220cU;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index 5bbb3b9fb..80663c2e5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -1396,6 +1396,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
 	return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
index 3ebed7ea0..ac8290134 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h
@@ -1508,6 +1508,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
 	return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
index f7bc4c23a..89c6bbaed 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h
@@ -1584,6 +1584,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
 	return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
index 0f83d6ba9..3955a63de 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
@@ -1816,6 +1816,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
 	return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index f7d8089d8..4a3da79e4 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -2420,6 +2420,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
 {
 	return 0x00502400U;
 }
+static inline u32 gr_gpc0_gpccs_ctxsw_mailbox__size_1_v(void)
+{
+	return 0x00000010U;
+}
 static inline u32 gr_fecs_ctxsw_idlestate_r(void)
 {
 	return 0x00409420U;