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gpu: nvgpu: Nvlink interrupt handling
Enable logging and error reporting for MIF, DLPL, and TLC blocks. Configure the NVLIPT and IOCTRL interrupt registers to rollup the MIF and TLC errors on the link-specific fatal line and the DLPL interrupts on link-specific intr_a(fatal) line. Both link_err_fatal and link_intr_a are rolled up to stall interrupt line. In the handling ISR, clear the interrupt status registers and print an error. Move the interrupt handling HAL code to /common/hal. JIRA NVGPU-4350 JIRA NVGPU-4351 JIRA NVGPU-5231 JIRA NVGPU-4354 JIRA NVGPU-4355 JIRA NVGPU-4356 Change-Id: I14812499caf506592f3ae84d6681d857730d31ff Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
committed by
Alex Waterman
Alex Waterman
parent
d58d6ff321
commit
5af8cedf05
@@ -1,511 +0,0 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef CONFIG_NVGPU_NVLINK
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include "intr_and_err_handling_gv100.h"
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#include <nvgpu/hw/gv100/hw_nvlipt_gv100.h>
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#include <nvgpu/hw/gv100/hw_ioctrl_gv100.h>
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#include <nvgpu/hw/gv100/hw_nvl_gv100.h>
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#include <nvgpu/hw/gv100/hw_ioctrlmif_gv100.h>
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#include <nvgpu/hw/gv100/hw_nvtlc_gv100.h>
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/*
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* The manuals are missing some useful defines
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* we add them for now
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*/
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#define IPT_INTR_CONTROL_LINK(i) (nvlipt_intr_control_link0_r() + (i)*4U)
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#define IPT_ERR_UC_STATUS_LINK(i) (nvlipt_err_uc_status_link0_r() + (i)*36U)
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#define IPT_ERR_UC_MASK_LINK(i) (nvlipt_err_uc_mask_link0_r() + (i)*36U)
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#define IPT_ERR_UC_SEVERITY_LINK(i) (nvlipt_err_uc_severity_link0_r() + (i)*36U)
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#define IPT_ERR_UC_FIRST_LINK(i) (nvlipt_err_uc_first_link0_r() + (i)*36U)
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#define IPT_ERR_UC_ADVISORY_LINK(i) (nvlipt_err_uc_advisory_link0_r() + (i)*36U)
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#define IPT_ERR_C_STATUS_LINK(i) (nvlipt_err_c_status_link0_r() + (i)*36U)
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#define IPT_ERR_C_MASK_LINK(i) (nvlipt_err_c_mask_link0_r() + (i)*36U)
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#define IPT_ERR_C_FIRST_LINK(i) (nvlipt_err_c_first_link0_r() + (i)*36U)
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#define IPT_ERR_CONTROL_LINK(i) (nvlipt_err_control_link0_r() + (i)*4U)
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#define IPT_ERR_UC_ACTIVE_BITS (nvlipt_err_uc_status_link0_dlprotocol_f(1) | \
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nvlipt_err_uc_status_link0_datapoisoned_f(1) | \
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nvlipt_err_uc_status_link0_flowcontrol_f(1) | \
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nvlipt_err_uc_status_link0_responsetimeout_f(1) | \
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nvlipt_err_uc_status_link0_targeterror_f(1) | \
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nvlipt_err_uc_status_link0_unexpectedresponse_f(1) | \
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nvlipt_err_uc_status_link0_receiveroverflow_f(1) | \
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nvlipt_err_uc_status_link0_malformedpacket_f(1) | \
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nvlipt_err_uc_status_link0_stompedpacketreceived_f(1) | \
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nvlipt_err_uc_status_link0_unsupportedrequest_f(1) | \
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nvlipt_err_uc_status_link0_ucinternal_f(1))
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/*
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* Init TLC per link interrupts
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*/
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static void gv100_nvlink_tlc_intr_enable(struct gk20a *g, u32 link_id,
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bool enable)
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{
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u32 reg_rx0 = 0, reg_rx1 = 0, reg_tx = 0;
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if (enable) {
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/* Set PROD values */
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reg_rx0 = 0x0FFFFFF;
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reg_rx1 = 0x03FFFFF;
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reg_tx = 0x1FFFFFF;
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}
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TLC_REG_WR32(g, link_id, nvtlc_rx_err_report_en_0_r(), reg_rx0);
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TLC_REG_WR32(g, link_id, nvtlc_rx_err_report_en_1_r(), reg_rx1);
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TLC_REG_WR32(g, link_id, nvtlc_tx_err_report_en_0_r(), reg_tx);
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}
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/*
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* helper function to get TLC intr status in common structure
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*/
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static void gv100_nvlink_tlc_get_intr(struct gk20a *g, u32 link_id)
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{
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g->nvlink.tlc_rx_err_status_0[link_id] =
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TLC_REG_RD32(g, link_id, nvtlc_rx_err_status_0_r());
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g->nvlink.tlc_rx_err_status_1[link_id] =
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TLC_REG_RD32(g, link_id, nvtlc_rx_err_status_1_r());
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g->nvlink.tlc_tx_err_status_0[link_id] =
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TLC_REG_RD32(g, link_id, nvtlc_tx_err_status_0_r());
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}
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/*
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* Interrupt routine handler for TLC
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*/
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static void gv100_nvlink_tlc_isr(struct gk20a *g, u32 link_id)
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{
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if (g->nvlink.tlc_rx_err_status_0[link_id] != 0U) {
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/* All TLC RX 0 errors are fatal. Notify and disable */
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nvgpu_err(g, "Fatal TLC RX 0 interrupt on link %d mask: %x",
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link_id, g->nvlink.tlc_rx_err_status_0[link_id]);
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TLC_REG_WR32(g, link_id, nvtlc_rx_err_first_0_r(),
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g->nvlink.tlc_rx_err_status_0[link_id]);
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TLC_REG_WR32(g, link_id, nvtlc_rx_err_status_0_r(),
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g->nvlink.tlc_rx_err_status_0[link_id]);
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}
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if (g->nvlink.tlc_rx_err_status_1[link_id] != 0U) {
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/* All TLC RX 1 errors are fatal. Notify and disable */
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nvgpu_err(g, "Fatal TLC RX 1 interrupt on link %d mask: %x",
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link_id, g->nvlink.tlc_rx_err_status_1[link_id]);
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TLC_REG_WR32(g, link_id, nvtlc_rx_err_first_1_r(),
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g->nvlink.tlc_rx_err_status_1[link_id]);
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TLC_REG_WR32(g, link_id, nvtlc_rx_err_status_1_r(),
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g->nvlink.tlc_rx_err_status_1[link_id]);
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}
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if (g->nvlink.tlc_tx_err_status_0[link_id] != 0U) {
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/* All TLC TX 0 errors are fatal. Notify and disable */
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nvgpu_err(g, "Fatal TLC TX 0 interrupt on link %d mask: %x",
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link_id, g->nvlink.tlc_tx_err_status_0[link_id]);
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TLC_REG_WR32(g, link_id, nvtlc_tx_err_first_0_r(),
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g->nvlink.tlc_tx_err_status_0[link_id]);
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TLC_REG_WR32(g, link_id, nvtlc_tx_err_status_0_r(),
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g->nvlink.tlc_tx_err_status_0[link_id]);
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}
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}
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/*
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* DLPL interrupt enable helper
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*/
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void gv100_nvlink_dlpl_intr_enable(struct gk20a *g, u32 link_id, bool enable)
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{
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u32 reg = 0;
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/* Always disable nonstall tree */
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DLPL_REG_WR32(g, link_id, nvl_intr_nonstall_en_r(), 0);
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if (!enable)
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{
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DLPL_REG_WR32(g, link_id, nvl_intr_stall_en_r(), 0);
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return;
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}
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/* Clear interrupt register to get rid of stale state (W1C) */
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DLPL_REG_WR32(g, link_id, nvl_intr_r(), 0xffffffffU);
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DLPL_REG_WR32(g, link_id, nvl_intr_sw2_r(), 0xffffffffU);
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reg = nvl_intr_stall_en_tx_recovery_long_enable_f() |
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nvl_intr_stall_en_tx_fault_ram_enable_f() |
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nvl_intr_stall_en_tx_fault_interface_enable_f() |
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nvl_intr_stall_en_tx_fault_sublink_change_enable_f() |
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nvl_intr_stall_en_rx_fault_sublink_change_enable_f() |
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nvl_intr_stall_en_rx_fault_dl_protocol_enable_f() |
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nvl_intr_stall_en_ltssm_fault_enable_f();
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DLPL_REG_WR32(g, link_id, nvl_intr_stall_en_r(), reg);
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/* Configure error threshold */
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reg = DLPL_REG_RD32(g, link_id, nvl_sl1_error_rate_ctrl_r());
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reg = set_field(reg, nvl_sl1_error_rate_ctrl_short_threshold_man_m(),
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nvl_sl1_error_rate_ctrl_short_threshold_man_f(0x2));
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reg = set_field(reg, nvl_sl1_error_rate_ctrl_long_threshold_man_m(),
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nvl_sl1_error_rate_ctrl_long_threshold_man_f(0x2));
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DLPL_REG_WR32(g, link_id, nvl_sl1_error_rate_ctrl_r(), reg);
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}
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/*
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* DLPL per-link isr
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*/
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#define DLPL_NON_FATAL_INTR_MASK (nvl_intr_tx_replay_f(1) | \
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nvl_intr_tx_recovery_short_f(1) | \
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nvl_intr_tx_recovery_long_f(1) | \
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nvl_intr_rx_short_error_rate_f(1) | \
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nvl_intr_rx_long_error_rate_f(1) | \
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nvl_intr_rx_ila_trigger_f(1) | \
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nvl_intr_ltssm_protocol_f(1))
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#define DLPL_FATAL_INTR_MASK ( nvl_intr_ltssm_fault_f(1) | \
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nvl_intr_rx_fault_dl_protocol_f(1) | \
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nvl_intr_rx_fault_sublink_change_f(1) | \
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nvl_intr_tx_fault_sublink_change_f(1) | \
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nvl_intr_tx_fault_interface_f(1) | \
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nvl_intr_tx_fault_ram_f(1))
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static void gv100_nvlink_dlpl_isr(struct gk20a *g, u32 link_id)
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{
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u32 non_fatal_mask = 0;
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u32 fatal_mask = 0;
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u32 intr = 0;
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bool retrain = false;
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int err;
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intr = DLPL_REG_RD32(g, link_id, nvl_intr_r()) &
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DLPL_REG_RD32(g, link_id, nvl_intr_stall_en_r());
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if (intr == 0U) {
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return;
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}
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fatal_mask = intr & DLPL_FATAL_INTR_MASK;
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non_fatal_mask = intr & DLPL_NON_FATAL_INTR_MASK;
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nvgpu_err(g, " handling DLPL %d isr. Fatal: %x non-Fatal: %x",
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link_id, fatal_mask, non_fatal_mask);
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/* Check if we are not handling an interupt */
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if (((fatal_mask | non_fatal_mask) & ~intr) != 0U) {
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nvgpu_err(g, "Unable to service DLPL intr on link %d", link_id);
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}
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if ((non_fatal_mask & nvl_intr_tx_recovery_long_f(1)) != 0U) {
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retrain = true;
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}
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if (fatal_mask != 0U) {
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retrain = false;
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}
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if (retrain) {
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err = nvgpu_nvlink_train(g, link_id, false);
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if (err != 0) {
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nvgpu_err(g, "failed to retrain link %d", link_id);
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}
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}
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/* Clear interrupts */
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DLPL_REG_WR32(g, link_id, nvl_intr_r(), (non_fatal_mask | fatal_mask));
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DLPL_REG_WR32(g, link_id, nvl_intr_sw2_r(), 0xffffffffU);
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}
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/*
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* Initialize MIF API with PROD settings
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*/
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void gv100_nvlink_init_mif_intr(struct gk20a *g, u32 link_id)
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{
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u32 tmp;
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/* Enable MIF RX error */
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/* Containment (make fatal) */
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tmp = 0;
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tmp = set_field(tmp,
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ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(),
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ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f());
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tmp = set_field(tmp,
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ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(),
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ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f());
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MIF_REG_WR32(g, link_id, ioctrlmif_rx_err_contain_en_0_r(), tmp);
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/* Logging (do not ignore) */
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tmp = 0;
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tmp = set_field(tmp,
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ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(),
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ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(1));
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tmp = set_field(tmp,
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ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(),
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ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(1));
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MIF_REG_WR32(g, link_id, ioctrlmif_rx_err_log_en_0_r(), tmp);
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/* Tx Error */
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/* Containment (make fatal) */
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tmp = 0;
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tmp = set_field(tmp,
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ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(),
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ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f());
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tmp = set_field(tmp,
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ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(),
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ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f());
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MIF_REG_WR32(g, link_id, ioctrlmif_tx_err_contain_en_0_r(), tmp);
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/* Logging (do not ignore) */
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tmp = 0;
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tmp = set_field(tmp, ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(),
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ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(1));
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tmp = set_field(tmp, ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(),
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ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(1));
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MIF_REG_WR32(g, link_id, ioctrlmif_tx_err_log_en_0_r(), tmp);
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/* Credit release */
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MIF_REG_WR32(g, link_id, ioctrlmif_rx_ctrl_buffer_ready_r(), 0x1);
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MIF_REG_WR32(g, link_id, ioctrlmif_tx_ctrl_buffer_ready_r(), 0x1);
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}
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/*
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* Enable per-link MIF interrupts
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*/
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void gv100_nvlink_mif_intr_enable(struct gk20a *g, u32 link_id, bool enable)
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{
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u32 reg0 = 0, reg1 = 0;
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if (enable) {
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reg0 = set_field(reg0,
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ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(),
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ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(1));
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reg0 = set_field(reg0,
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ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(),
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ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(1));
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reg1 = set_field(reg1,
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ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(),
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ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(1));
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reg1 = set_field(reg1,
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ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(),
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ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(1));
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}
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MIF_REG_WR32(g, link_id, ioctrlmif_rx_err_report_en_0_r(), reg0);
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MIF_REG_WR32(g, link_id, ioctrlmif_tx_err_report_en_0_r(), reg1);
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}
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/*
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* Handle per-link MIF interrupts
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*/
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static void gv100_nvlink_mif_isr(struct gk20a *g, u32 link_id)
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{
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u32 intr, fatal_mask = 0;
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/* RX Errors */
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intr = MIF_REG_RD32(g, link_id, ioctrlmif_rx_err_status_0_r());
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if (intr != 0U) {
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if ((intr & ioctrlmif_rx_err_status_0_rxramdataparityerr_m()) !=
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0U) {
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nvgpu_err(g, "Fatal MIF RX interrupt hit on link %d: RAM_DATA_PARITY",
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link_id);
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fatal_mask |= ioctrlmif_rx_err_status_0_rxramdataparityerr_f(1);
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}
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if ((intr & ioctrlmif_rx_err_status_0_rxramhdrparityerr_m()) !=
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0U) {
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nvgpu_err(g, "Fatal MIF RX interrupt hit on link %d: RAM_HDR_PARITY",
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link_id);
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fatal_mask |= ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(1);
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}
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if (fatal_mask != 0U) {
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MIF_REG_WR32(g, link_id, ioctrlmif_rx_err_first_0_r(),
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fatal_mask);
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MIF_REG_WR32(g, link_id, ioctrlmif_rx_err_status_0_r(),
|
||||
fatal_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/* TX Errors */
|
||||
fatal_mask = 0;
|
||||
intr = MIF_REG_RD32(g, link_id, ioctrlmif_tx_err_status_0_r());
|
||||
if (intr != 0U) {
|
||||
if ((intr & ioctrlmif_tx_err_status_0_txramdataparityerr_m()) !=
|
||||
0U) {
|
||||
nvgpu_err(g, "Fatal MIF TX interrupt hit on link %d: RAM_DATA_PARITY",
|
||||
link_id);
|
||||
fatal_mask |= ioctrlmif_tx_err_status_0_txramdataparityerr_f(1);
|
||||
}
|
||||
if ((intr & ioctrlmif_tx_err_status_0_txramhdrparityerr_m()) !=
|
||||
0U) {
|
||||
nvgpu_err(g, "Fatal MIF TX interrupt hit on link %d: RAM_HDR_PARITY",
|
||||
link_id);
|
||||
fatal_mask |= ioctrlmif_tx_err_status_0_txramhdrparityerr_f(1);
|
||||
}
|
||||
|
||||
if (fatal_mask != 0U) {
|
||||
MIF_REG_WR32(g, link_id, ioctrlmif_tx_err_first_0_r(),
|
||||
fatal_mask);
|
||||
MIF_REG_WR32(g, link_id, ioctrlmif_tx_err_status_0_r(),
|
||||
fatal_mask);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* NVLIPT IP initialization (per-link)
|
||||
*/
|
||||
void gv100_nvlink_init_nvlipt_intr(struct gk20a *g, u32 link_id)
|
||||
{
|
||||
/* init persistent scratch registers */
|
||||
IPT_REG_WR32(g, nvlipt_scratch_cold_r(),
|
||||
nvlipt_scratch_cold_data_init_v());
|
||||
|
||||
/*
|
||||
* AErr settings (top level)
|
||||
*/
|
||||
|
||||
/* UC first and status reg (W1C) need to be cleared byt arch */
|
||||
IPT_REG_WR32(g, IPT_ERR_UC_FIRST_LINK(link_id), IPT_ERR_UC_ACTIVE_BITS);
|
||||
IPT_REG_WR32(g, IPT_ERR_UC_STATUS_LINK(link_id), IPT_ERR_UC_ACTIVE_BITS);
|
||||
|
||||
/* AErr Severity */
|
||||
IPT_REG_WR32(g, IPT_ERR_UC_SEVERITY_LINK(link_id), IPT_ERR_UC_ACTIVE_BITS);
|
||||
|
||||
/* AErr Control settings */
|
||||
IPT_REG_WR32(g, IPT_ERR_CONTROL_LINK(link_id),
|
||||
nvlipt_err_control_link0_fatalenable_f(1) |
|
||||
nvlipt_err_control_link0_nonfatalenable_f(1));
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable NVLIPT interrupts
|
||||
*/
|
||||
static void gv100_nvlink_nvlipt_intr_enable(struct gk20a *g, u32 link_id,
|
||||
bool enable)
|
||||
{
|
||||
u32 val = 0;
|
||||
u32 reg;
|
||||
|
||||
if (enable) {
|
||||
val = 1;
|
||||
}
|
||||
|
||||
reg = IPT_REG_RD32(g, IPT_INTR_CONTROL_LINK(link_id));
|
||||
reg = set_field(reg, nvlipt_intr_control_link0_stallenable_m(),
|
||||
nvlipt_intr_control_link0_stallenable_f(val));
|
||||
reg = set_field(reg, nvlipt_intr_control_link0_nostallenable_m(),
|
||||
nvlipt_intr_control_link0_nostallenable_f(val));
|
||||
IPT_REG_WR32(g, IPT_INTR_CONTROL_LINK(link_id), reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Per-link NVLIPT ISR handler
|
||||
*/
|
||||
static void gv100_nvlink_nvlipt_isr(struct gk20a *g, u32 link_id)
|
||||
{
|
||||
/*
|
||||
* Interrupt handling happens in leaf handlers. Assume all interrupts
|
||||
* were handled and clear roll ups/
|
||||
*/
|
||||
IPT_REG_WR32(g, IPT_ERR_UC_FIRST_LINK(link_id), IPT_ERR_UC_ACTIVE_BITS);
|
||||
IPT_REG_WR32(g, IPT_ERR_UC_STATUS_LINK(link_id), IPT_ERR_UC_ACTIVE_BITS);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Interrupt handling functions *
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* Enable common interrupts
|
||||
*/
|
||||
void gv100_nvlink_common_intr_enable(struct gk20a *g, unsigned long mask)
|
||||
{
|
||||
u32 reg, link_id;
|
||||
unsigned long bit;
|
||||
|
||||
/* Init IOCTRL */
|
||||
for_each_set_bit(bit, &mask, NVLINK_MAX_LINKS_SW) {
|
||||
link_id = (u32)bit;
|
||||
reg = IOCTRL_REG_RD32(g, ioctrl_link_intr_0_mask_r(link_id));
|
||||
reg |= (ioctrl_link_intr_0_mask_fatal_f(1) |
|
||||
ioctrl_link_intr_0_mask_nonfatal_f(1) |
|
||||
ioctrl_link_intr_0_mask_correctable_f(1) |
|
||||
ioctrl_link_intr_0_mask_intra_f(1));
|
||||
IOCTRL_REG_WR32(g, ioctrl_link_intr_0_mask_r(link_id), reg);
|
||||
}
|
||||
|
||||
reg = IOCTRL_REG_RD32(g, ioctrl_common_intr_0_mask_r());
|
||||
reg |= (ioctrl_common_intr_0_mask_fatal_f(1) |
|
||||
ioctrl_common_intr_0_mask_nonfatal_f(1) |
|
||||
ioctrl_common_intr_0_mask_correctable_f(1) |
|
||||
ioctrl_common_intr_0_mask_intra_f(1));
|
||||
IOCTRL_REG_WR32(g, ioctrl_common_intr_0_mask_r(), reg);
|
||||
|
||||
/* Init NVLIPT */
|
||||
IPT_REG_WR32(g, nvlipt_intr_control_common_r(),
|
||||
nvlipt_intr_control_common_stallenable_f(1) |
|
||||
nvlipt_intr_control_common_nonstallenable_f(1));
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable link specific interrupts (top-level)
|
||||
*/
|
||||
void gv100_nvlink_enable_link_intr(struct gk20a *g, u32 link_id, bool enable)
|
||||
{
|
||||
g->ops.nvlink.minion.enable_link_intr(g, link_id, enable);
|
||||
gv100_nvlink_dlpl_intr_enable(g, link_id, enable);
|
||||
gv100_nvlink_tlc_intr_enable(g, link_id, enable);
|
||||
gv100_nvlink_mif_intr_enable(g, link_id, enable);
|
||||
gv100_nvlink_nvlipt_intr_enable(g, link_id, enable);
|
||||
}
|
||||
|
||||
/*
|
||||
* Top level interrupt handler
|
||||
*/
|
||||
void gv100_nvlink_isr(struct gk20a *g)
|
||||
{
|
||||
unsigned long links;
|
||||
u32 link_id;
|
||||
unsigned long bit;
|
||||
|
||||
links = ioctrl_top_intr_0_status_link_v(
|
||||
IOCTRL_REG_RD32(g, ioctrl_top_intr_0_status_r()));
|
||||
|
||||
links &= g->nvlink.enabled_links;
|
||||
/* As per ARCH minion must be serviced first */
|
||||
g->ops.nvlink.minion.isr(g);
|
||||
|
||||
for_each_set_bit(bit, &links, NVLINK_MAX_LINKS_SW) {
|
||||
link_id = (u32)bit;
|
||||
/* Cache error logs from TLC, DL handler may clear them */
|
||||
gv100_nvlink_tlc_get_intr(g, link_id);
|
||||
gv100_nvlink_dlpl_isr(g, link_id);
|
||||
gv100_nvlink_tlc_isr(g, link_id);
|
||||
gv100_nvlink_mif_isr(g, link_id);
|
||||
|
||||
/* NVLIPT is top-level. Do it last */
|
||||
gv100_nvlink_nvlipt_isr(g, link_id);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_NVGPU_NVLINK */
|
||||
@@ -1,37 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef INTR_AND_ERR_HANDLING_GV100_H
|
||||
#define INTR_AND_ERR_HANDLING_GV100_H
|
||||
|
||||
#include <nvgpu/types.h>
|
||||
struct gk20a;
|
||||
|
||||
void gv100_nvlink_common_intr_enable(struct gk20a *g, unsigned long mask);
|
||||
void gv100_nvlink_init_nvlipt_intr(struct gk20a *g, u32 link_id);
|
||||
void gv100_nvlink_enable_link_intr(struct gk20a *g, u32 link_id, bool enable);
|
||||
void gv100_nvlink_init_mif_intr(struct gk20a *g, u32 link_id);
|
||||
void gv100_nvlink_mif_intr_enable(struct gk20a *g, u32 link_id, bool enable);
|
||||
void gv100_nvlink_dlpl_intr_enable(struct gk20a *g, u32 link_id, bool enable);
|
||||
void gv100_nvlink_isr(struct gk20a *g);
|
||||
|
||||
#endif /* INTR_AND_ERR_HANDLING_GV100_H */
|
||||
@@ -57,9 +57,6 @@ u32 gv100_nvlink_get_link_reset_mask(struct gk20a *g)
|
||||
|
||||
static int gv100_nvlink_state_load_hal(struct gk20a *g)
|
||||
{
|
||||
unsigned long discovered = g->nvlink.discovered_links;
|
||||
|
||||
g->ops.nvlink.intr.common_intr_enable(g, discovered);
|
||||
return nvgpu_nvlink_minion_load(g);
|
||||
}
|
||||
|
||||
@@ -254,8 +251,8 @@ static int gv100_nvlink_enable_links_post_top(struct gk20a *g,
|
||||
if (g->ops.nvlink.set_sw_war != NULL) {
|
||||
g->ops.nvlink.set_sw_war(g, link_id);
|
||||
}
|
||||
g->ops.nvlink.intr.init_nvlipt_intr(g, link_id);
|
||||
g->ops.nvlink.intr.enable_link_intr(g, link_id, true);
|
||||
g->ops.nvlink.intr.init_link_err_intr(g, link_id);
|
||||
g->ops.nvlink.intr.enable_link_err_intr(g, link_id, true);
|
||||
|
||||
g->nvlink.initialized_links |= BIT32(link_id);
|
||||
};
|
||||
@@ -766,16 +763,7 @@ int gv100_nvlink_link_early_init(struct gk20a *g, unsigned long mask)
|
||||
|
||||
int gv100_nvlink_interface_init(struct gk20a *g)
|
||||
{
|
||||
unsigned long mask = g->nvlink.enabled_links;
|
||||
u32 link_id;
|
||||
int err;
|
||||
unsigned long bit;
|
||||
|
||||
for_each_set_bit(bit, &mask, NVLINK_MAX_LINKS_SW) {
|
||||
link_id = (u32)bit;
|
||||
g->ops.nvlink.intr.init_mif_intr(g, link_id);
|
||||
g->ops.nvlink.intr.mif_intr_enable(g, link_id, true);
|
||||
}
|
||||
|
||||
err = g->ops.fb.init_nvlink(g);
|
||||
if (err != 0) {
|
||||
|
||||
Reference in New Issue
Block a user