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git://nv-tegra.nvidia.com/linux-nvgpu.git
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gpu: nvgpu: Nvlink interrupt handling
Enable logging and error reporting for MIF, DLPL, and TLC blocks. Configure the NVLIPT and IOCTRL interrupt registers to rollup the MIF and TLC errors on the link-specific fatal line and the DLPL interrupts on link-specific intr_a(fatal) line. Both link_err_fatal and link_intr_a are rolled up to stall interrupt line. In the handling ISR, clear the interrupt status registers and print an error. Move the interrupt handling HAL code to /common/hal. JIRA NVGPU-4350 JIRA NVGPU-4351 JIRA NVGPU-5231 JIRA NVGPU-4354 JIRA NVGPU-4355 JIRA NVGPU-4356 Change-Id: I14812499caf506592f3ae84d6681d857730d31ff Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
committed by
Alex Waterman
Alex Waterman
parent
d58d6ff321
commit
5af8cedf05
@@ -575,16 +575,9 @@ struct gpu_ops {
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bool (*is_debug_mode)(struct gk20a *g);
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} minion;
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struct {
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void (*common_intr_enable)(struct gk20a *g,
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unsigned long mask);
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void (*init_nvlipt_intr)(struct gk20a *g, u32 link_id);
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void (*enable_link_intr)(struct gk20a *g, u32 link_id,
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bool enable);
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void (*init_mif_intr)(struct gk20a *g, u32 link_id);
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void (*mif_intr_enable)(struct gk20a *g, u32 link_id,
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bool enable);
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void (*dlpl_intr_enable)(struct gk20a *g, u32 link_id,
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bool enable);
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void (*init_link_err_intr)(struct gk20a *g, u32 link_id);
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void (*enable_link_err_intr)(struct gk20a *g,
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u32 link_id, bool enable);
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void (*isr)(struct gk20a *g);
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} intr;
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} nvlink;
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -122,7 +122,7 @@
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#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(v) ((U32(v) & 0x1U) << 1U)
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#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m() (U32(0x1U) << 1U)
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#define ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(r) (((r) >> 1U) & 0x1U)
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#define ioctrlmif_tx_err_report_en_0_r() (0x00000e08U)
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#define ioctrlmif_tx_err_report_en_0_r() (0x00000a8cU)
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#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(v)\
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((U32(v) & 0x1U) << 0U)
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#define ioctrlmif_tx_err_report_en_0_txramdataparityerr_m() (U32(0x1U) << 0U)
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@@ -143,4 +143,8 @@
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#define ioctrlmif_tx_err_first_0_r() (0x00000a98U)
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#define ioctrlmif_tx_ctrl_buffer_ready_r() (0x00000a7cU)
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#define ioctrlmif_rx_ctrl_buffer_ready_r() (0x00000dfcU)
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#define ioctrlmif_tx_err_misc_0_r() (0x00000a9cU)
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#define ioctrlmif_tx_err_misc_0_txramdataparitypois_f(v) ((U32(v) & 0x1U) << 0U)
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#define ioctrlmif_tx_err_misc_0_txramdataparitypois_m() (U32(0x1U) << 0U)
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#define ioctrlmif_tx_err_misc_0_txramdataparitypois_v(r) (((r) >> 0U) & 0x1U)
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#endif
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -256,9 +256,25 @@
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#define nvl_sl1_error_rate_ctrl_short_threshold_man_f(v) ((U32(v) & 0x7U) << 0U)
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#define nvl_sl1_error_rate_ctrl_short_threshold_man_m() (U32(0x7U) << 0U)
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#define nvl_sl1_error_rate_ctrl_short_threshold_man_v(r) (((r) >> 0U) & 0x7U)
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#define nvl_sl1_error_rate_ctrl_short_threshold_exp_f(v) ((U32(v) & 0x1U) << 3U)
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#define nvl_sl1_error_rate_ctrl_short_threshold_exp_m() (U32(0x1U) << 3U)
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#define nvl_sl1_error_rate_ctrl_short_threshold_exp_v(r) (((r) >> 3U) & 0x1U)
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#define nvl_sl1_error_rate_ctrl_long_threshold_man_f(v) ((U32(v) & 0x7U) << 16U)
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#define nvl_sl1_error_rate_ctrl_long_threshold_man_m() (U32(0x7U) << 16U)
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#define nvl_sl1_error_rate_ctrl_long_threshold_man_v(r) (((r) >> 16U) & 0x7U)
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#define nvl_sl1_error_rate_ctrl_short_timescale_man_f(v) ((U32(v) & 0x7U) << 4U)
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#define nvl_sl1_error_rate_ctrl_short_timescale_man_m() (U32(0x7U) << 4U)
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#define nvl_sl1_error_rate_ctrl_short_timescale_man_v(r) (((r) >> 4U) & 0x7U)
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#define nvl_sl1_error_rate_ctrl_short_timescale_exp_f(v) ((U32(v) & 0xfU) << 8U)
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#define nvl_sl1_error_rate_ctrl_short_timescale_exp_m() (U32(0xfU) << 8U)
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#define nvl_sl1_error_rate_ctrl_short_timescale_exp_v(r) (((r) >> 8U) & 0xfU)
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#define nvl_sl1_error_count_ctrl_r() (0x00003280U)
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#define nvl_sl1_error_count_ctrl_short_rate_f(v) ((U32(v) & 0x1U) << 8U)
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#define nvl_sl1_error_count_ctrl_short_rate_m() (U32(0x1U) << 8U)
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#define nvl_sl1_error_count_ctrl_short_rate_enable_f() (0x100U)
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#define nvl_sl1_error_count_ctrl_rate_count_mode_f(v) ((U32(v) & 0x1U) << 10U)
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#define nvl_sl1_error_count_ctrl_rate_count_mode_m() (U32(0x1U) << 10U)
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#define nvl_sl1_error_count_ctrl_rate_count_mode_flit_f() (0x0U)
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#define nvl_sl1_rxslsm_timeout_2_r() (0x00003034U)
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#define nvl_txiobist_configreg_r() (0x00002e14U)
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#define nvl_txiobist_configreg_io_bist_mode_in_f(v) ((U32(v) & 0x1U) << 17U)
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -59,13 +59,257 @@
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#include <nvgpu/types.h>
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#include <nvgpu/static_analysis.h>
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#define nvtlc_tx_err_report_en_0_r() (0x00000708U)
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#define nvtlc_rx_err_report_en_0_r() (0x00000f08U)
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#define nvtlc_rx_err_report_en_1_r() (0x00000f20U)
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#define nvtlc_tx_err_status_0_r() (0x00000700U)
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#define nvtlc_rx_err_status_0_r() (0x00000f00U)
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#define nvtlc_rx_err_status_1_r() (0x00000f18U)
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#define nvtlc_tx_err_first_0_r() (0x00000714U)
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#define nvtlc_rx_err_first_0_r() (0x00000f14U)
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#define nvtlc_rx_err_first_1_r() (0x00000f2cU)
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#define nvtlc_tx_err_report_en_0_r() (0x00000708U)
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#define nvtlc_tx_err_report_en_0_txhdrcreditovferr_f(v) ((U32(v) & 0xffU) << 0U)
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#define nvtlc_tx_err_report_en_0_txhdrcreditovferr__prod_f() (0xffU)
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#define nvtlc_tx_err_report_en_0_txdatacreditovferr_f(v)\
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((U32(v) & 0xffU) << 8U)
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#define nvtlc_tx_err_report_en_0_txdatacreditovferr__prod_f() (0xff00U)
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#define nvtlc_tx_err_report_en_0_txdlcreditovferr_f(v) ((U32(v) & 0x1U) << 16U)
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#define nvtlc_tx_err_report_en_0_txdlcreditovferr__prod_f() (0x10000U)
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#define nvtlc_tx_err_report_en_0_txdlcreditparityerr_f(v)\
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((U32(v) & 0x1U) << 17U)
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#define nvtlc_tx_err_report_en_0_txdlcreditparityerr__prod_f() (0x20000U)
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#define nvtlc_tx_err_report_en_0_txramhdrparityerr_f(v) ((U32(v) & 0x1U) << 18U)
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#define nvtlc_tx_err_report_en_0_txramhdrparityerr__prod_f() (0x40000U)
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#define nvtlc_tx_err_report_en_0_txramdataparityerr_f(v)\
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((U32(v) & 0x1U) << 19U)
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#define nvtlc_tx_err_report_en_0_txramdataparityerr__prod_f() (0x80000U)
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#define nvtlc_tx_err_report_en_0_txunsupvcovferr_f(v) ((U32(v) & 0x1U) << 20U)
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#define nvtlc_tx_err_report_en_0_txunsupvcovferr__prod_f() (0x100000U)
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#define nvtlc_tx_err_report_en_0_txstompdet_f(v) ((U32(v) & 0x1U) << 22U)
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#define nvtlc_tx_err_report_en_0_txstompdet__prod_f() (0x400000U)
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#define nvtlc_tx_err_report_en_0_txpoisondet_f(v) ((U32(v) & 0x1U) << 23U)
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#define nvtlc_tx_err_report_en_0_txpoisondet__prod_f() (0x800000U)
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#define nvtlc_tx_err_report_en_0_targeterr_f(v) ((U32(v) & 0x1U) << 24U)
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#define nvtlc_tx_err_report_en_0_targeterr__prod_f() (0x1000000U)
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#define nvtlc_tx_err_report_en_0_unsupportedrequesterr_f(v)\
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((U32(v) & 0x1U) << 25U)
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#define nvtlc_tx_err_report_en_0_unsupportedrequesterr__prod_f() (0x2000000U)
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#define nvtlc_tx_err_log_en_0_r() (0x00000704U)
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#define nvtlc_tx_err_log_en_0_txhdrcreditovferr_f(v) ((U32(v) & 0xffU) << 0U)
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#define nvtlc_tx_err_log_en_0_txhdrcreditovferr__prod_f() (0xffU)
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#define nvtlc_tx_err_log_en_0_txdatacreditovferr_f(v) ((U32(v) & 0xffU) << 8U)
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#define nvtlc_tx_err_log_en_0_txdatacreditovferr__prod_f() (0xff00U)
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#define nvtlc_tx_err_log_en_0_txdlcreditovferr_f(v) ((U32(v) & 0x1U) << 16U)
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#define nvtlc_tx_err_log_en_0_txdlcreditovferr__prod_f() (0x10000U)
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#define nvtlc_tx_err_log_en_0_txdlcreditparityerr_f(v) ((U32(v) & 0x1U) << 17U)
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#define nvtlc_tx_err_log_en_0_txdlcreditparityerr__prod_f() (0x20000U)
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#define nvtlc_tx_err_log_en_0_txramhdrparityerr_f(v) ((U32(v) & 0x1U) << 18U)
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#define nvtlc_tx_err_log_en_0_txramhdrparityerr__prod_f() (0x40000U)
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#define nvtlc_tx_err_log_en_0_txramdataparityerr_f(v) ((U32(v) & 0x1U) << 19U)
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#define nvtlc_tx_err_log_en_0_txramdataparityerr__prod_f() (0x80000U)
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#define nvtlc_tx_err_log_en_0_txunsupvcovferr_f(v) ((U32(v) & 0x1U) << 20U)
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#define nvtlc_tx_err_log_en_0_txunsupvcovferr__prod_f() (0x100000U)
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#define nvtlc_tx_err_log_en_0_txstompdet_f(v) ((U32(v) & 0x1U) << 22U)
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#define nvtlc_tx_err_log_en_0_txstompdet__prod_f() (0x400000U)
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#define nvtlc_tx_err_log_en_0_txpoisondet_f(v) ((U32(v) & 0x1U) << 23U)
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#define nvtlc_tx_err_log_en_0_txpoisondet__prod_f() (0x800000U)
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#define nvtlc_tx_err_log_en_0_targeterr_f(v) ((U32(v) & 0x1U) << 24U)
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#define nvtlc_tx_err_log_en_0_targeterr__prod_f() (0x1000000U)
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#define nvtlc_tx_err_log_en_0_unsupportedrequesterr_f(v)\
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((U32(v) & 0x1U) << 25U)
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#define nvtlc_tx_err_log_en_0_unsupportedrequesterr__prod_f() (0x2000000U)
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#define nvtlc_tx_err_contain_en_0_r() (0x0000070cU)
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#define nvtlc_tx_err_contain_en_0_txhdrcreditovferr_f(v)\
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((U32(v) & 0xffU) << 0U)
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#define nvtlc_tx_err_contain_en_0_txhdrcreditovferr__prod_f() (0xffU)
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#define nvtlc_tx_err_contain_en_0_txdatacreditovferr_f(v)\
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((U32(v) & 0xffU) << 8U)
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#define nvtlc_tx_err_contain_en_0_txdatacreditovferr__prod_f() (0xff00U)
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#define nvtlc_tx_err_contain_en_0_txdlcreditovferr_f(v) ((U32(v) & 0x1U) << 16U)
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#define nvtlc_tx_err_contain_en_0_txdlcreditovferr__prod_f() (0x10000U)
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#define nvtlc_tx_err_contain_en_0_txdlcreditparityerr_f(v)\
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((U32(v) & 0x1U) << 17U)
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#define nvtlc_tx_err_contain_en_0_txdlcreditparityerr__prod_f() (0x20000U)
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#define nvtlc_tx_err_contain_en_0_txramhdrparityerr_f(v)\
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((U32(v) & 0x1U) << 18U)
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#define nvtlc_tx_err_contain_en_0_txramhdrparityerr__prod_f() (0x40000U)
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#define nvtlc_tx_err_contain_en_0_txunsupvcovferr_f(v) ((U32(v) & 0x1U) << 20U)
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#define nvtlc_tx_err_contain_en_0_txunsupvcovferr__prod_f() (0x100000U)
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#define nvtlc_tx_err_contain_en_0_txstompdet_f(v) ((U32(v) & 0x1U) << 22U)
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#define nvtlc_tx_err_contain_en_0_txstompdet__prod_f() (0x400000U)
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#define nvtlc_tx_err_contain_en_0_txpoisondet_f(v) ((U32(v) & 0x1U) << 23U)
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#define nvtlc_tx_err_contain_en_0_targeterr_f(v) ((U32(v) & 0x1U) << 24U)
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#define nvtlc_tx_err_contain_en_0_unsupportedrequesterr_f(v)\
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((U32(v) & 0x1U) << 25U)
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#define nvtlc_rx_err_report_en_0_r() (0x00000f08U)
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#define nvtlc_rx_err_report_en_0_rxdlhdrparityerr_f(v) ((U32(v) & 0x1U) << 0U)
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#define nvtlc_rx_err_report_en_0_rxdlhdrparityerr__prod_f() (0x1U)
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#define nvtlc_rx_err_report_en_0_rxdldataparityerr_f(v) ((U32(v) & 0x1U) << 1U)
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#define nvtlc_rx_err_report_en_0_rxdldataparityerr__prod_f() (0x2U)
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#define nvtlc_rx_err_report_en_0_rxdlctrlparityerr_f(v) ((U32(v) & 0x1U) << 2U)
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#define nvtlc_rx_err_report_en_0_rxdlctrlparityerr__prod_f() (0x4U)
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#define nvtlc_rx_err_report_en_0_rxramdataparityerr_f(v) ((U32(v) & 0x1U) << 3U)
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#define nvtlc_rx_err_report_en_0_rxramdataparityerr__prod_f() (0x8U)
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#define nvtlc_rx_err_report_en_0_rxramhdrparityerr_f(v) ((U32(v) & 0x1U) << 4U)
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#define nvtlc_rx_err_report_en_0_rxramhdrparityerr__prod_f() (0x10U)
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#define nvtlc_rx_err_report_en_0_rxinvalidaeerr_f(v) ((U32(v) & 0x1U) << 5U)
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#define nvtlc_rx_err_report_en_0_rxinvalidaeerr__prod_f() (0x20U)
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#define nvtlc_rx_err_report_en_0_rxinvalidbeerr_f(v) ((U32(v) & 0x1U) << 6U)
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#define nvtlc_rx_err_report_en_0_rxinvalidbeerr__prod_f() (0x40U)
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#define nvtlc_rx_err_report_en_0_rxinvalidaddralignerr_f(v)\
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((U32(v) & 0x1U) << 7U)
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#define nvtlc_rx_err_report_en_0_rxinvalidaddralignerr__prod_f() (0x80U)
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#define nvtlc_rx_err_report_en_0_rxpktlenerr_f(v) ((U32(v) & 0x1U) << 8U)
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#define nvtlc_rx_err_report_en_0_rxpktlenerr__prod_f() (0x100U)
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#define nvtlc_rx_err_report_en_0_datlengtatomicreqmaxerr_f(v)\
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((U32(v) & 0x1U) << 17U)
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#define nvtlc_rx_err_report_en_0_datlengtatomicreqmaxerr__prod_f() (0x20000U)
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#define nvtlc_rx_err_report_en_0_datlengtrmwreqmaxerr_f(v)\
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((U32(v) & 0x1U) << 18U)
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#define nvtlc_rx_err_report_en_0_datlengtrmwreqmaxerr__prod_f() (0x40000U)
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#define nvtlc_rx_err_report_en_0_datlenltatrrspminerr_f(v)\
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((U32(v) & 0x1U) << 19U)
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#define nvtlc_rx_err_report_en_0_datlenltatrrspminerr__prod_f() (0x80000U)
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#define nvtlc_rx_err_report_en_0_invalidcacheattrpoerr_f(v)\
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((U32(v) & 0x1U) << 20U)
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#define nvtlc_rx_err_report_en_0_invalidcacheattrpoerr__prod_f() (0x100000U)
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#define nvtlc_rx_err_report_en_0_invalidcrerr_f(v) ((U32(v) & 0x1U) << 21U)
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#define nvtlc_rx_err_report_en_0_invalidcrerr__prod_f() (0x200000U)
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#define nvtlc_rx_err_report_en_0_rxrespstatustargeterr_f(v)\
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((U32(v) & 0x1U) << 22U)
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#define nvtlc_rx_err_report_en_0_rxrespstatustargeterr__prod_f() (0x400000U)
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#define nvtlc_rx_err_report_en_0_rxrespstatusunsupportedrequesterr_f(v)\
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((U32(v) & 0x1U) << 23U)
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#define nvtlc_rx_err_report_en_0_rxrespstatusunsupportedrequesterr__prod_f()\
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(0x800000U)
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#define nvtlc_rx_err_log_en_0_r() (0x00000f04U)
|
||||
#define nvtlc_rx_err_log_en_0_rxdlhdrparityerr_f(v) ((U32(v) & 0x1U) << 0U)
|
||||
#define nvtlc_rx_err_log_en_0_rxdlhdrparityerr__prod_f() (0x1U)
|
||||
#define nvtlc_rx_err_log_en_0_rxdldataparityerr_f(v) ((U32(v) & 0x1U) << 1U)
|
||||
#define nvtlc_rx_err_log_en_0_rxdldataparityerr__prod_f() (0x2U)
|
||||
#define nvtlc_rx_err_log_en_0_rxdlctrlparityerr_f(v) ((U32(v) & 0x1U) << 2U)
|
||||
#define nvtlc_rx_err_log_en_0_rxdlctrlparityerr__prod_f() (0x4U)
|
||||
#define nvtlc_rx_err_log_en_0_rxramdataparityerr_f(v) ((U32(v) & 0x1U) << 3U)
|
||||
#define nvtlc_rx_err_log_en_0_rxramdataparityerr__prod_f() (0x8U)
|
||||
#define nvtlc_rx_err_log_en_0_rxramhdrparityerr_f(v) ((U32(v) & 0x1U) << 4U)
|
||||
#define nvtlc_rx_err_log_en_0_rxramhdrparityerr__prod_f() (0x10U)
|
||||
#define nvtlc_rx_err_log_en_0_rxinvalidaeerr_f(v) ((U32(v) & 0x1U) << 5U)
|
||||
#define nvtlc_rx_err_log_en_0_rxinvalidaeerr__prod_f() (0x20U)
|
||||
#define nvtlc_rx_err_log_en_0_rxinvalidbeerr_f(v) ((U32(v) & 0x1U) << 6U)
|
||||
#define nvtlc_rx_err_log_en_0_rxinvalidbeerr__prod_f() (0x40U)
|
||||
#define nvtlc_rx_err_log_en_0_rxinvalidaddralignerr_f(v) ((U32(v) & 0x1U) << 7U)
|
||||
#define nvtlc_rx_err_log_en_0_rxinvalidaddralignerr__prod_f() (0x80U)
|
||||
#define nvtlc_rx_err_log_en_0_rxpktlenerr_f(v) ((U32(v) & 0x1U) << 8U)
|
||||
#define nvtlc_rx_err_log_en_0_rxpktlenerr__prod_f() (0x100U)
|
||||
#define nvtlc_rx_err_log_en_0_datlengtatomicreqmaxerr_f(v)\
|
||||
((U32(v) & 0x1U) << 17U)
|
||||
#define nvtlc_rx_err_log_en_0_datlengtatomicreqmaxerr__prod_f() (0x20000U)
|
||||
#define nvtlc_rx_err_log_en_0_datlengtrmwreqmaxerr_f(v) ((U32(v) & 0x1U) << 18U)
|
||||
#define nvtlc_rx_err_log_en_0_datlengtrmwreqmaxerr__prod_f() (0x40000U)
|
||||
#define nvtlc_rx_err_log_en_0_datlenltatrrspminerr_f(v) ((U32(v) & 0x1U) << 19U)
|
||||
#define nvtlc_rx_err_log_en_0_datlenltatrrspminerr__prod_f() (0x80000U)
|
||||
#define nvtlc_rx_err_log_en_0_invalidcacheattrpoerr_f(v)\
|
||||
((U32(v) & 0x1U) << 20U)
|
||||
#define nvtlc_rx_err_log_en_0_invalidcacheattrpoerr__prod_f() (0x100000U)
|
||||
#define nvtlc_rx_err_log_en_0_invalidcrerr_f(v) ((U32(v) & 0x1U) << 21U)
|
||||
#define nvtlc_rx_err_log_en_0_invalidcrerr__prod_f() (0x200000U)
|
||||
#define nvtlc_rx_err_log_en_0_rxrespstatustargeterr_f(v)\
|
||||
((U32(v) & 0x1U) << 22U)
|
||||
#define nvtlc_rx_err_log_en_0_rxrespstatustargeterr__prod_f() (0x400000U)
|
||||
#define nvtlc_rx_err_log_en_0_rxrespstatusunsupportedrequesterr_f(v)\
|
||||
((U32(v) & 0x1U) << 23U)
|
||||
#define nvtlc_rx_err_log_en_0_rxrespstatusunsupportedrequesterr__prod_f()\
|
||||
(0x800000U)
|
||||
#define nvtlc_rx_err_contain_en_0_r() (0x00000f0cU)
|
||||
#define nvtlc_rx_err_contain_en_0_rxdlhdrparityerr_f(v) ((U32(v) & 0x1U) << 0U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxdlhdrparityerr__prod_f() (0x1U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxdldataparityerr_f(v) ((U32(v) & 0x1U) << 1U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxdldataparityerr__prod_f() (0x2U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxdlctrlparityerr_f(v) ((U32(v) & 0x1U) << 2U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxdlctrlparityerr__prod_f() (0x4U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxramdataparityerr_f(v)\
|
||||
((U32(v) & 0x1U) << 3U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxramhdrparityerr_f(v) ((U32(v) & 0x1U) << 4U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxramhdrparityerr__prod_f() (0x10U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxinvalidaeerr_f(v) ((U32(v) & 0x1U) << 5U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxinvalidaeerr__prod_f() (0x20U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxinvalidbeerr_f(v) ((U32(v) & 0x1U) << 6U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxinvalidbeerr__prod_f() (0x40U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxinvalidaddralignerr_f(v)\
|
||||
((U32(v) & 0x1U) << 7U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxinvalidaddralignerr__prod_f() (0x80U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxpktlenerr_f(v) ((U32(v) & 0x1U) << 8U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxpktlenerr__prod_f() (0x100U)
|
||||
#define nvtlc_rx_err_contain_en_0_datlengtatomicreqmaxerr_f(v)\
|
||||
((U32(v) & 0x1U) << 17U)
|
||||
#define nvtlc_rx_err_contain_en_0_datlengtatomicreqmaxerr__prod_f() (0x20000U)
|
||||
#define nvtlc_rx_err_contain_en_0_datlengtrmwreqmaxerr_f(v)\
|
||||
((U32(v) & 0x1U) << 18U)
|
||||
#define nvtlc_rx_err_contain_en_0_datlengtrmwreqmaxerr__prod_f() (0x40000U)
|
||||
#define nvtlc_rx_err_contain_en_0_datlenltatrrspminerr_f(v)\
|
||||
((U32(v) & 0x1U) << 19U)
|
||||
#define nvtlc_rx_err_contain_en_0_datlenltatrrspminerr__prod_f() (0x80000U)
|
||||
#define nvtlc_rx_err_contain_en_0_invalidcacheattrpoerr_f(v)\
|
||||
((U32(v) & 0x1U) << 20U)
|
||||
#define nvtlc_rx_err_contain_en_0_invalidcacheattrpoerr__prod_f() (0x100000U)
|
||||
#define nvtlc_rx_err_contain_en_0_invalidcrerr_f(v) ((U32(v) & 0x1U) << 21U)
|
||||
#define nvtlc_rx_err_contain_en_0_invalidcrerr__prod_f() (0x200000U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxrespstatustargeterr_f(v)\
|
||||
((U32(v) & 0x1U) << 22U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxrespstatustargeterr__prod_f() (0x400000U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxrespstatusunsupportedrequesterr_f(v)\
|
||||
((U32(v) & 0x1U) << 23U)
|
||||
#define nvtlc_rx_err_contain_en_0_rxrespstatusunsupportedrequesterr__prod_f()\
|
||||
(0x800000U)
|
||||
#define nvtlc_rx_err_report_en_1_r() (0x00000f20U)
|
||||
#define nvtlc_rx_err_report_en_1_rxhdrovferr_f(v) ((U32(v) & 0xffU) << 0U)
|
||||
#define nvtlc_rx_err_report_en_1_rxhdrovferr__prod_f() (0xffU)
|
||||
#define nvtlc_rx_err_report_en_1_rxdataovferr_f(v) ((U32(v) & 0xffU) << 8U)
|
||||
#define nvtlc_rx_err_report_en_1_rxdataovferr__prod_f() (0xff00U)
|
||||
#define nvtlc_rx_err_report_en_1_stompdeterr_f(v) ((U32(v) & 0x1U) << 16U)
|
||||
#define nvtlc_rx_err_report_en_1_stompdeterr__prod_f() (0x10000U)
|
||||
#define nvtlc_rx_err_report_en_1_rxpoisonerr_f(v) ((U32(v) & 0x1U) << 17U)
|
||||
#define nvtlc_rx_err_report_en_1_rxpoisonerr__prod_f() (0x20000U)
|
||||
#define nvtlc_rx_err_report_en_1_rxunsupvcovferr_f(v) ((U32(v) & 0x1U) << 19U)
|
||||
#define nvtlc_rx_err_report_en_1_rxunsupvcovferr__prod_f() (0x80000U)
|
||||
#define nvtlc_rx_err_report_en_1_rxunsupnvlinkcreditrelerr_f(v)\
|
||||
((U32(v) & 0x1U) << 20U)
|
||||
#define nvtlc_rx_err_report_en_1_rxunsupnvlinkcreditrelerr__prod_f() (0x100000U)
|
||||
#define nvtlc_rx_err_report_en_1_rxunsupncisoccreditrelerr_f(v)\
|
||||
((U32(v) & 0x1U) << 21U)
|
||||
#define nvtlc_rx_err_report_en_1_rxunsupncisoccreditrelerr__prod_f() (0x200000U)
|
||||
#define nvtlc_rx_err_log_en_1_r() (0x00000f1cU)
|
||||
#define nvtlc_rx_err_log_en_1_rxhdrovferr_f(v) ((U32(v) & 0xffU) << 0U)
|
||||
#define nvtlc_rx_err_log_en_1_rxhdrovferr__prod_f() (0xffU)
|
||||
#define nvtlc_rx_err_log_en_1_rxdataovferr_f(v) ((U32(v) & 0xffU) << 8U)
|
||||
#define nvtlc_rx_err_log_en_1_rxdataovferr__prod_f() (0xff00U)
|
||||
#define nvtlc_rx_err_log_en_1_stompdeterr_f(v) ((U32(v) & 0x1U) << 16U)
|
||||
#define nvtlc_rx_err_log_en_1_stompdeterr__prod_f() (0x10000U)
|
||||
#define nvtlc_rx_err_log_en_1_rxpoisonerr_f(v) ((U32(v) & 0x1U) << 17U)
|
||||
#define nvtlc_rx_err_log_en_1_rxpoisonerr__prod_f() (0x20000U)
|
||||
#define nvtlc_rx_err_log_en_1_rxunsupvcovferr_f(v) ((U32(v) & 0x1U) << 19U)
|
||||
#define nvtlc_rx_err_log_en_1_rxunsupvcovferr__prod_f() (0x80000U)
|
||||
#define nvtlc_rx_err_log_en_1_rxunsupnvlinkcreditrelerr_f(v)\
|
||||
((U32(v) & 0x1U) << 20U)
|
||||
#define nvtlc_rx_err_log_en_1_rxunsupnvlinkcreditrelerr__prod_f() (0x100000U)
|
||||
#define nvtlc_rx_err_log_en_1_rxunsupncisoccreditrelerr_f(v)\
|
||||
((U32(v) & 0x1U) << 21U)
|
||||
#define nvtlc_rx_err_log_en_1_rxunsupncisoccreditrelerr__prod_f() (0x200000U)
|
||||
#define nvtlc_rx_err_contain_en_1_r() (0x00000f24U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxhdrovferr_f(v) ((U32(v) & 0xffU) << 0U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxhdrovferr__prod_f() (0xffU)
|
||||
#define nvtlc_rx_err_contain_en_1_rxdataovferr_f(v) ((U32(v) & 0xffU) << 8U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxdataovferr__prod_f() (0xff00U)
|
||||
#define nvtlc_rx_err_contain_en_1_stompdeterr_f(v) ((U32(v) & 0x1U) << 16U)
|
||||
#define nvtlc_rx_err_contain_en_1_stompdeterr__prod_f() (0x10000U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxpoisonerr_f(v) ((U32(v) & 0x1U) << 17U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxpoisonerr__prod_f() (0x20000U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxunsupvcovferr_f(v) ((U32(v) & 0x1U) << 19U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxunsupvcovferr__prod_f() (0x80000U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxunsupnvlinkcreditrelerr_f(v)\
|
||||
((U32(v) & 0x1U) << 20U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxunsupnvlinkcreditrelerr__prod_f()\
|
||||
(0x100000U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxunsupncisoccreditrelerr_f(v)\
|
||||
((U32(v) & 0x1U) << 21U)
|
||||
#define nvtlc_rx_err_contain_en_1_rxunsupncisoccreditrelerr__prod_f()\
|
||||
(0x200000U)
|
||||
#endif
|
||||
|
||||
@@ -182,7 +182,6 @@ int nvgpu_nvlink_interface_init(struct gk20a *g);
|
||||
int nvgpu_nvlink_interface_disable(struct gk20a *g);
|
||||
int nvgpu_nvlink_dev_shutdown(struct gk20a *g);
|
||||
int nvgpu_nvlink_enumerate(struct gk20a *g);
|
||||
int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off);
|
||||
int nvgpu_nvlink_remove(struct gk20a *g);
|
||||
void nvgpu_mss_nvlink_init_credits(struct gk20a *g);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user