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gpu: nvgpu: handle SM reported MMU_NACK exception

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Upon receiving MMU_FAULT error, MMU will forward MMU_NACK to SM
If MMU_NACK is masked out, SM will simply release the semaphores

And if semaphores are released before MMU fault is handled, user space
could see that operation as successful incorrectly

Fix this by handling SM reported MMU_NACK exception

Enable MMU_NACK reporting in gv11b_gr_set_hww_esr_report_mask

In MMU_NACK handling path, we just set the error notifier and clear
the interrupt so that the User Space sees the error as soon as
semaphores are released by SM
And MMU_FAULT handling path will take care of triggering RC recovery
anyways

Also add necessary h/w accessors for mmu_nack

Bug 2040594
Jira NVGPU-473

Change-Id: Ic925c2d3f3069016c57d177713066c29ab39dc3d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631708
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-01-04 05:02:46 -08:00
committed by mobile promotions
parent 6170f1eed5
commit 5b10690479
3 changed files with 61 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -3344,6 +3344,10 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_repor
{
return 0x400000U;
}
static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void)
{
return 0x4000000U;
}
static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
{
return 0x00419d0cU;
@@ -3552,6 +3556,10 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void)
{
return 0x00000000U;
}
static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void)
{
return 0x20U;
}
static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void)
{
return 0x0U;

10
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -3940,6 +3940,10 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_repor
{
return 0x400000U;
}
static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void)
{
return 0x4000000U;
}
static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
{
return 0x00419d0cU;
@@ -4240,6 +4244,10 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void)
{
return 0x0U;
}
static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void)
{
return 0x20U;
}
static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void)
{
return 0xffU << 16U;