gpu: nvgpu: skip subctx pdb init during as-channel bind

While creating a new channel, ioctls are called in the below sequence:
  1. GPU_IOCTL_OPEN_CHANNEL
  2. AS_IOCTL_BIND_CHANNEL
  3. TSG_IOCTL_BIND_CHANNEL_EX
  4. CHANNEL_ALLOC_GPFIFO_EX
  5. CHANNEL_ALLOC_OBJ_CTX.

subctx pdbs and valid mask are programmed in the channel instance block
in the channel ioctls AS_IOCTL_BIND_CHANNEL & CHANNEL_ALLOC_GPFIFO_EX.

Programming them in the ioctl AS_IOCTL_BIND_CHANNEL is redundant.
Remove related hal g->ops.mm.init_inst_block_for_subctxs.

The hal init_inst_block will program context pdb and big page size.
The hal init_inst_block_core will program context pdb, big page size
and subctx 0 pdb. This is used by h/w units (fecs, pmu, hwpm, bar1,
bar2, sec2, gsp, perfbuf etc.).

For user channels, subctx pdbs are programmed as part of ramfc setup.

Bug 3677982

Change-Id: I6656b002d513404c1fd7c3d349933e80cca7e604
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2680907
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/channel.c

@@ -148,19 +148,8 @@ void nvgpu_channel_commit_va(struct nvgpu_channel *c)
 
 	nvgpu_log_fn(g, " ");
 
-	if (g->ops.mm.init_inst_block_for_subctxs != NULL) {
-		u32 subctx_count = nvgpu_channel_get_max_subctx_count(c);
-
-		nvgpu_log(g, gpu_dbg_info | gpu_dbg_mig,
-			"chid: %d max_subctx_count[%u] ",
-			c->chid, subctx_count);
-		g->ops.mm.init_inst_block_for_subctxs(&c->inst_block, c->vm,
-				c->vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG],
-				subctx_count);
-	} else {
 	g->ops.mm.init_inst_block(&c->inst_block, c->vm,
 			c->vm->gmmu_page_sizes[GMMU_PAGE_SIZE_BIG]);
-	}
 }
 
 int nvgpu_channel_update_runlist(struct nvgpu_channel *c, bool add)

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -227,7 +227,7 @@ static int nvgpu_gr_falcon_init_ctxsw_ucode_vaspace(struct gk20a *g,
 		return err;
 	}
 
-	g->ops.mm.init_inst_block(&ucode_info->inst_blk_desc, vm, 0);
+	g->ops.mm.init_inst_block_core(&ucode_info->inst_blk_desc, vm, 0);
 
 	/* Map ucode surface to GMMU */
 	ucode_info->surface_desc.gpu_va = nvgpu_gmmu_map(vm,

drivers/gpu/nvgpu/common/mm/mm.c

@@ -228,7 +228,7 @@ static int nvgpu_init_system_vm(struct mm_gk20a *mm)
 	if (err != 0) {
 		goto clean_up_vm;
 	}
-	g->ops.mm.init_inst_block(inst_block, mm->pmu.vm, big_page_size);
+	g->ops.mm.init_inst_block_core(inst_block, mm->pmu.vm, big_page_size);
 
 	return 0;
 
@@ -247,7 +247,7 @@ static int nvgpu_init_hwpm(struct mm_gk20a *mm)
 	if (err != 0) {
 		return err;
 	}
-	g->ops.mm.init_inst_block(inst_block, mm->pmu.vm, 0);
+	g->ops.mm.init_inst_block_core(inst_block, mm->pmu.vm, 0);
 
 	return 0;
 }
@@ -366,7 +366,7 @@ static int nvgpu_init_bar1_vm(struct mm_gk20a *mm)
 	if (err != 0) {
 		goto clean_up_vm;
 	}
-	g->ops.mm.init_inst_block(inst_block, mm->bar1.vm, big_page_size);
+	g->ops.mm.init_inst_block_core(inst_block, mm->bar1.vm, big_page_size);
 
 	return 0;
 
@@ -401,7 +401,7 @@ static int nvgpu_init_engine_ucode_vm(struct gk20a *g,
 		goto clean_up_va;
 	}
 
-	g->ops.mm.init_inst_block(inst_block, ucode->vm, big_page_size);
+	g->ops.mm.init_inst_block_core(inst_block, ucode->vm, big_page_size);
 
 	return 0;
 

drivers/gpu/nvgpu/common/perf/perfbuf.c

@@ -72,7 +72,7 @@ int nvgpu_perfbuf_init_inst_block(struct gk20a *g)
 		return err;
 	}
 
-	g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0);
+	g->ops.mm.init_inst_block_core(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0);
 	g->ops.perf.init_inst_block(g, &mm->perfbuf.inst_block);
 
 	return 0;

drivers/gpu/nvgpu/hal/init/hal_ga100.c

@@ -1270,7 +1270,7 @@ static const struct gops_mm ga100_ops_mm = {
 	.setup_hw = nvgpu_mm_setup_hw,
 	.is_bar1_supported = gv11b_mm_is_bar1_supported,
 	.init_inst_block = gv11b_mm_init_inst_block,
-	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_inst_block_core = gv11b_mm_init_inst_block_core,
 	.init_bar2_vm = gp10b_mm_init_bar2_vm,
 	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 	.get_flush_retries = tu104_mm_get_flush_retries,

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -1281,7 +1281,7 @@ static const struct gops_mm ga10b_ops_mm = {
 	.setup_hw = nvgpu_mm_setup_hw,
 	.is_bar1_supported = gv11b_mm_is_bar1_supported,
 	.init_inst_block = gv11b_mm_init_inst_block,
-	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_inst_block_core = gv11b_mm_init_inst_block_core,
 	.init_bar2_vm = gp10b_mm_init_bar2_vm,
 	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 	.get_default_va_sizes = gp10b_mm_get_default_va_sizes,

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -803,6 +803,7 @@ static const struct gops_mm gm20b_ops_mm = {
 	.setup_hw = nvgpu_mm_setup_hw,
 	.is_bar1_supported = gm20b_mm_is_bar1_supported,
 	.init_inst_block = gk20a_mm_init_inst_block,
+	.init_inst_block_core = gk20a_mm_init_inst_block,
 	.get_default_va_sizes = gm20b_mm_get_default_va_sizes,
 #ifdef CONFIG_NVGPU_USERD
 	.bar1_map_userd = gk20a_mm_bar1_map_userd,

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -1101,7 +1101,7 @@ static const struct gops_mm gv11b_ops_mm = {
 	.setup_hw = nvgpu_mm_setup_hw,
 	.is_bar1_supported = gv11b_mm_is_bar1_supported,
 	.init_inst_block = gv11b_mm_init_inst_block,
-	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_inst_block_core = gv11b_mm_init_inst_block_core,
 	.init_bar2_vm = gp10b_mm_init_bar2_vm,
 	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 	.get_default_va_sizes = gp10b_mm_get_default_va_sizes,

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1157,7 +1157,7 @@ static const struct gops_mm tu104_ops_mm = {
 	.setup_hw = nvgpu_mm_setup_hw,
 	.is_bar1_supported = gv11b_mm_is_bar1_supported,
 	.init_inst_block = gv11b_mm_init_inst_block,
-	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_inst_block_core = gv11b_mm_init_inst_block_core,
 	.init_bar2_vm = gp10b_mm_init_bar2_vm,
 	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 	.get_flush_retries = tu104_mm_get_flush_retries,

drivers/gpu/nvgpu/hal/mm/mm_gp10b_fusa.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -51,7 +51,7 @@ int gp10b_mm_init_bar2_vm(struct gk20a *g)
 		goto clean_up_va;
 	}
 
-	g->ops.mm.init_inst_block(inst_block, mm->bar2.vm, big_page_size);
+	g->ops.mm.init_inst_block_core(inst_block, mm->bar2.vm, big_page_size);
 
 	return 0;
 

drivers/gpu/nvgpu/hal/mm/mm_gv11b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,8 +30,9 @@ struct vm_gk20a;
 
 void gv11b_mm_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm,
 			      u32 big_page_size);
-void gv11b_mm_init_inst_block_for_subctxs(struct nvgpu_mem *inst_block,
+void gv11b_mm_init_inst_block_core(struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm, u32 big_page_size, u32 max_subctx_count);
+				   struct vm_gk20a *vm,
+				   u32 big_page_size);
 bool gv11b_mm_is_bar1_supported(struct gk20a *g);
 
 #endif

drivers/gpu/nvgpu/hal/mm/mm_gv11b_fusa.c

@@ -40,33 +40,16 @@ void gv11b_mm_init_inst_block(struct nvgpu_mem *inst_block,
 	if ((big_page_size != 0U) && (g->ops.ramin.set_big_page_size != NULL)) {
 		g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
 	}
-
-	if (g->ops.ramin.init_subctx_pdb != NULL) {
-		g->ops.ramin.init_subctx_pdb(g, inst_block, vm->pdb.mem, false,
-			1U);
-	}
 }
 
-void gv11b_mm_init_inst_block_for_subctxs(struct nvgpu_mem *inst_block,
+void gv11b_mm_init_inst_block_core(struct nvgpu_mem *inst_block,
-		struct vm_gk20a *vm, u32 big_page_size, u32 max_subctx_count)
+		struct vm_gk20a *vm, u32 big_page_size)
 {
 	struct gk20a *g = gk20a_from_vm(vm);
-	u64 pdb_addr = nvgpu_pd_gpu_addr(g, &vm->pdb);
 
-	nvgpu_log_info(g, "inst block phys = 0x%llx, kv = 0x%p",
+	gv11b_mm_init_inst_block(inst_block, vm, big_page_size);
-		nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va);
 
-	g->ops.ramin.init_pdb(g, inst_block, pdb_addr, vm->pdb.mem);
+	g->ops.ramin.init_subctx_pdb(g, inst_block, vm->pdb.mem, false, 1U);
-
-	if ((big_page_size != 0U) &&
-			(g->ops.ramin.set_big_page_size != NULL)) {
-		g->ops.ramin.set_big_page_size(g, inst_block, big_page_size);
-	}
-
-	if (g->ops.ramin.init_subctx_pdb != NULL) {
-		g->ops.ramin.init_subctx_pdb(g, inst_block, vm->pdb.mem, false,
-			max_subctx_count);
-	}
 }
 
 bool gv11b_mm_is_bar1_supported(struct gk20a *g)

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c

@@ -809,7 +809,7 @@ static const struct gops_mm vgpu_ga10b_ops_mm = {
 	.setup_hw = NULL,
 	.is_bar1_supported = gv11b_mm_is_bar1_supported,
 	.init_inst_block = gv11b_mm_init_inst_block,
-	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_inst_block_core = gv11b_mm_init_inst_block_core,
 	.init_bar2_vm = gp10b_mm_init_bar2_vm,
 	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 	.vm_as_alloc_share = vgpu_vm_as_alloc_share,

drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c

@@ -778,7 +778,7 @@ static const struct gops_mm vgpu_gv11b_ops_mm = {
 	.setup_hw = NULL,
 	.is_bar1_supported = gv11b_mm_is_bar1_supported,
 	.init_inst_block = gv11b_mm_init_inst_block,
-	.init_inst_block_for_subctxs = gv11b_mm_init_inst_block_for_subctxs,
+	.init_inst_block_core = gv11b_mm_init_inst_block_core,
 	.init_bar2_vm = gp10b_mm_init_bar2_vm,
 	.remove_bar2_vm = gp10b_mm_remove_bar2_vm,
 	.bar1_map_userd = NULL,

drivers/gpu/nvgpu/include/nvgpu/gops/mm.h

@@ -539,35 +539,35 @@ struct gops_mm {
 	void (*remove_bar2_vm)(struct gk20a *g);
 
 	/**
-	 * @brief HAL to initialize the instance block memory.
+	 * @brief HAL to initialize the instance block memory for user channels.
 	 *
-	 * @param inst_block    [in]	Pointer to instance block memory.
+	 * @param inst_block    [in]	Pointer to channel instance block
+	 *                              memory.
 	 * @param vm            [in]	Pointer to virtual memory context.
 	 * @param big_page_size [in]	Big page size supported by GMMU.
 	 *
 	 * Initializes the instance block memory:
-	 * - Configures the pdb base, big page size and
+	 * - Configures the pdb base, big page size in channel's instance block
-	 *   sub context's pdb base in context's instance block memory.
+	 *   memory.
 	 */
 	void (*init_inst_block)(struct nvgpu_mem *inst_block,
 			struct vm_gk20a *vm, u32 big_page_size);
 
 	/**
-	 * @brief HAL to initialize the instance block memory.
+	 * @brief HAL to initialize the instance block memory for GPU contexts
-	 * (for more than one subctx)
+	 *        for h/w units (fecs, pmu, hwpm, bar1, bar2, sec2, gsp and
+	 *        perfbuf).
 	 *
 	 * @param inst_block    [in]	Pointer to instance block memory.
 	 * @param vm            [in]	Pointer to virtual memory context.
 	 * @param big_page_size [in]	Big page size supported by GMMU.
-	 * @param max_subctx_count [in] Max number of sub context.
 	 *
 	 * Initializes the instance block memory:
 	 * - Configures the pdb base, big page size and
-	 *   sub context's pdb base in context's instance block memory.
+	 *   0th sub context's pdb base in context's instance block memory.
 	 */
-	void (*init_inst_block_for_subctxs)(struct nvgpu_mem *inst_block,
+	void (*init_inst_block_core)(struct nvgpu_mem *inst_block,
-			struct vm_gk20a *vm, u32 big_page_size,
+			struct vm_gk20a *vm, u32 big_page_size);
-			u32 max_subctx_count);
 
 	/**
 	 * @brief HAL to get the maximum flush retry counts.

userspace/units/mm/page_table_faults/page_table_faults.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -345,7 +345,7 @@ int test_page_faults_inst_block(struct unit_module *m, struct gk20a *g,
 		unit_return_fail(m, "nvgpu_alloc_inst_block failed\n");
 	}
 
-	g->ops.mm.init_inst_block(&inst_blk_desc, g->mm.bar2.vm, big_page_size);
+	g->ops.mm.init_inst_block_core(&inst_blk_desc, g->mm.bar2.vm, big_page_size);
 
 	return UNIT_SUCCESS;
 }