From 5bd62ba4c802f53d1feeb3976f353362c9054da4 Mon Sep 17 00:00:00 2001
From: vinodg <vinodg@nvidia.com>
Date: Tue, 1 Oct 2019 19:31:59 -0700
Subject: [PATCH] gpu: nvgpu: check for valid ctx in gr error report code

Add checking whether the current context is valid on reporting
sm exception error. This is needed as the interrupt unit test
call without a valid channel.

Jira NVGPU-4096

Change-Id: Ic6c49593dea26148f33f3bbf41a5dee437925c56
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2209873
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/common/gr/gr_intr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/nvgpu/common/gr/gr_intr.c b/drivers/gpu/nvgpu/common/gr/gr_intr.c
index c48a81b95..60f24b540 100644
--- a/drivers/gpu/nvgpu/common/gr/gr_intr.c
+++ b/drivers/gpu/nvgpu/common/gr/gr_intr.c
@@ -209,6 +209,10 @@ static void gr_intr_report_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
 	tsgid = NVGPU_INVALID_TSG_ID;
 	curr_ctx = g->ops.gr.falcon.get_current_ctx(g);
+	if (curr_ctx == 0U) {
+		return;
+	}
+
 	ch = nvgpu_gr_intr_get_channel_from_ctx(g, curr_ctx, &tsgid);
 	chid = ch != NULL ? ch->chid : NVGPU_INVALID_CHANNEL_ID;
 	if (ch != NULL) {