gpu: nvgpu: add IP audited FBPROUTER/GPCROUTER base and extents and NV_PLTCG_LTCS base

Added IP audited FBPRouter and GPCRouter Pri Register Ranges
and LTC Broadcast base addr

IP audit bug number: 3616021
Bug: 3442801

Change-Id: I52adc3bbb6b573377a9012db4b50bef51ef31e8a
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2714144
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
atanand
2022-05-20 09:21:42 +00:00
committed by mobile promotions
parent 2ebc0bdf98
commit 5c3d78dfb0
8 changed files with 22 additions and 7 deletions

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -61,6 +61,7 @@
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_pltcg_ltcs_base_v() (0x0017e000U)
#define ltc_ltc0_ltss_v() (0x00140200U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)

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@@ -60,6 +60,8 @@
#include <nvgpu/static_analysis.h>
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_pltcg_ltcs_base_v() (0x0017e000U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)
#define ltc_ltcs_ltss_tstg_set_mgmt0_r() (0x0017e2acU)

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -61,6 +61,7 @@
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_pltcg_ltcs_base_v() (0x0017e000U)
#define ltc_ltc0_ltss_v() (0x00140200U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -61,6 +61,7 @@
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_pltcg_ltcs_base_v() (0x0017e000U)
#define ltc_ltc0_ltss_v() (0x00140200U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -61,6 +61,7 @@
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_pltcg_ltcs_base_v() (0x0017e000U)
#define ltc_ltc0_ltss_v() (0x00140200U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -63,10 +63,14 @@
#define perf_pmmsys_perdomain_offset_v() (0x00000200U)
#define perf_pmmgpc_base_v() (0x00180000U)
#define perf_pmmgpc_extent_v() (0x00183fffU)
#define perf_pmmgpcrouter_base_v() (0x00244000U)
#define perf_pmmgpcrouter_extent_v() (0x002441ffU)
#define perf_pmmsys_base_v() (0x00240000U)
#define perf_pmmsys_extent_v() (0x00243fffU)
#define perf_pmmfbp_base_v() (0x00200000U)
#define perf_pmmfbp_extent_v() (0x00203fffU)
#define perf_pmmfbprouter_base_v() (0x00246000U)
#define perf_pmmfbprouter_extent_v() (0x002461ffU)
#define perf_pmasys_control_r() (0x0024a000U)
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -61,6 +61,7 @@
#define ltc_pltcg_base_v() (0x00140000U)
#define ltc_pltcg_extent_v() (0x0017ffffU)
#define ltc_pltcg_ltcs_base_v() (0x0017e000U)
#define ltc_ltc0_ltss_v() (0x00140200U)
#define ltc_ltc0_lts0_v() (0x00140400U)
#define ltc_ltcs_ltss_v() (0x0017e200U)

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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -63,10 +63,14 @@
#define perf_pmmsys_perdomain_offset_v() (0x00000200U)
#define perf_pmmgpc_base_v() (0x00180000U)
#define perf_pmmgpc_extent_v() (0x00183fffU)
#define perf_pmmgpcrouter_base_v() (0x00244000U)
#define perf_pmmgpcrouter_extent_v() (0x002441ffU)
#define perf_pmmsys_base_v() (0x00240000U)
#define perf_pmmsys_extent_v() (0x00243fffU)
#define perf_pmmfbp_base_v() (0x00200000U)
#define perf_pmmfbp_extent_v() (0x00203fffU)
#define perf_pmmfbprouter_base_v() (0x00246000U)
#define perf_pmmfbprouter_extent_v() (0x002461ffU)
#define perf_pmasys_control_r() (0x0024a000U)
#define perf_pmasys_control_membuf_status_v(r) (((r) >> 4U) & 0x1U)
#define perf_pmasys_control_membuf_status_overflowed_v() (0x00000001U)