From 5c7b73e6cacc9b90034fadf03197b6f97f8a252a Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Mon, 15 Jun 2020 10:24:54 -0700 Subject: [PATCH] gpu: nvgpu: update PLC enabled flag name Modify NVGPU_SUPPORT_PLC enabled flag name to NVGPU_SUPPORT_POST_L2_COMPRESSION keep name more specific. JIRA NVGPU-4666 Change-Id: I69336d74210457025921149768cfef036891bf72 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2361157 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/enabled.h | 2 +- drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 4 ++-- include/uapi/linux/nvgpu.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 8ffbcb4da..6bf3f7d2c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -259,7 +259,7 @@ struct gk20a; #define NVGPU_SUPPORT_SM_TTU 88U /** PLC Compression */ -#define NVGPU_SUPPORT_PLC 89U +#define NVGPU_SUPPORT_POST_L2_COMPRESSION 89U /* * Must be greater than the largest bit offset in the above list. diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index b0890bef8..d131f9b71 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -255,8 +255,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = { NVGPU_SUPPORT_COMPRESSION}, {NVGPU_GPU_FLAGS_SUPPORT_SM_TTU, NVGPU_SUPPORT_SM_TTU}, - {NVGPU_GPU_FLAGS_SUPPORT_PLC, - NVGPU_SUPPORT_PLC} + {NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION, + NVGPU_SUPPORT_POST_L2_COMPRESSION} }; static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index a3cb5630a..0bbebe972 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -178,7 +178,7 @@ struct nvgpu_gpu_zbc_query_table_args { /* SM TTU is enabled */ #define NVGPU_GPU_FLAGS_SUPPORT_SM_TTU (1ULL << 37) /* Compression PLC is enabled */ -#define NVGPU_GPU_FLAGS_SUPPORT_PLC (1ULL << 38) +#define NVGPU_GPU_FLAGS_SUPPORT_POST_L2_COMPRESSION (1ULL << 38) /* SM LRF ECC is enabled */ #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60) /* SM SHM ECC is enabled */