diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index e22da7301..7c9743ab6 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B ACR
  *
- * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef __ACR_GM20B_H_
-#define __ACR_GM20B_H_
+#ifndef NVGPU_GM20B_ACR_GM20B_H
+#define NVGPU_GM20B_ACR_GM20B_H
 
 #define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
 #define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
@@ -59,4 +59,4 @@ int acr_ucode_patch_sig(struct gk20a *g,
 		unsigned int *p_dbg_sig,
 		unsigned int *p_patch_loc,
 		unsigned int *p_patch_ind);
-#endif /*__ACR_GM20B_H_*/
+#endif /*NVGPU_GM20B_ACR_GM20B_H*/
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
index 09b1bdcc9..d67b280bc 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B Graphics
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef _NVHOST_CLK_GM20B_H_
-#define _NVHOST_CLK_GM20B_H_
+#ifndef NVGPU_GM20B_CLK_GM20B_H
+#define NVGPU_GM20B_CLK_GM20B_H
 
 #include <nvgpu/lock.h>
 
@@ -90,4 +90,4 @@ static inline u32 nvgpu_div_to_pl(u32 div)
 	return div;
 }
 
-#endif /* _NVHOST_CLK_GM20B_H_ */
+#endif /* NVGPU_GM20B_CLK_GM20B_H */
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
index f9e1f95d1..b9e207211 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVHOST_GM20B_FIFO
-#define _NVHOST_GM20B_FIFO
+#ifndef NVGPU_GM20B_FIFO_GM20B_H
+#define NVGPU_GM20B_FIFO_GM20B_H
 struct gk20a;
 struct mmu_fault_info;
 
@@ -38,4 +38,4 @@ void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
 void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
 void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault);
 
-#endif
+#endif /* NVGPU_GM20B_FIFO_GM20B_H */
diff --git a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h
index 8712b3539..d33a2591e 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B Graphics Context
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,8 +21,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __GR_CTX_GM20B_H__
-#define __GR_CTX_GM20B_H__
+#ifndef NVGPU_GM20B_GR_CTX_GM20B_H
+#define NVGPU_GM20B_GR_CTX_GM20B_H
 
 #include "gk20a/gr_ctx_gk20a.h"
 
@@ -33,4 +33,4 @@
 int gr_gm20b_get_netlist_name(struct gk20a *g, int index, char *name);
 bool gr_gm20b_is_firmware_defined(void);
 
-#endif /*__GR_CTX_GM20B_H__*/
+#endif /*NVGPU_GM20B_GR_CTX_GM20B_H*/
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 0f5dfe53c..0a486c2e8 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVHOST_GM20B_GR_MMU_H
-#define _NVHOST_GM20B_GR_MMU_H
+#ifndef NVGPU_GM20B_GR_GM20B_H
+#define NVGPU_GM20B_GR_GM20B_H
 
 struct gk20a;
 struct nvgpu_warpstate;
@@ -128,4 +128,4 @@ void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
 			u32 global_esr);
 u32 gr_gm20b_get_pmm_per_chiplet_offset(void);
 void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable);
-#endif
+#endif /* NVGPU_GM20B_GR_GM20B_H */
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h
index 22eae1824..5deb7ef57 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B Graphics
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,10 +22,10 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVHOST_HAL_GM20B_H
-#define _NVHOST_HAL_GM20B_H
+#ifndef NVGPU_GM20B_HAL_GM20B_H
+#define NVGPU_GM20B_HAL_GM20B_H
 struct gk20a;
 
 int gm20b_init_hal(struct gk20a *g);
 int gm20b_get_litter_value(struct gk20a *g, int value);
-#endif
+#endif /* NVGPU_GM20B_HAL_GM20B_H */
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
index 369fa1eb2..be10be383 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
@@ -20,8 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVHOST_GM20B_MM
-#define _NVHOST_GM20B_MM
+#ifndef NVGPU_GM20B_MM_GM20B_H
+#define NVGPU_GM20B_MM_GM20B_H
 struct gk20a;
 
 #define PDE_ADDR_START(x, y)	((x) &  ~((0x1UL << (y)) - 1))
@@ -37,4 +37,4 @@ u64 gm20b_gpu_phys_addr(struct gk20a *g,
 			struct nvgpu_gmmu_attrs *attrs, u64 phys);
 u32 gm20b_get_kind_invalid(void);
 u32 gm20b_get_kind_pitch(void);
-#endif
+#endif /* NVGPU_GM20B_MM_GM20B_H */
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
index 1923c047f..f1b6cd93e 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B PMU
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef __PMU_GM20B_H_
-#define __PMU_GM20B_H_
+#ifndef NVGPU_GM20B_PMU_GM20B_H
+#define NVGPU_GM20B_PMU_GM20B_H
 
 struct gk20a;
 
@@ -35,4 +35,4 @@ int gm20b_pmu_init_acr(struct gk20a *g);
 void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);
 bool gm20b_pmu_is_debug_mode_en(struct gk20a *g);
 
-#endif /*__PMU_GM20B_H_*/
+#endif /*NVGPU_GM20B_PMU_GM20B_H*/
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
index 99044f09c..11a35f895 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.h
@@ -22,8 +22,8 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef __REGOPS_GM20B_H_
-#define __REGOPS_GM20B_H_
+#ifndef NVGPU_GM20B_REGOPS_GM20B_H
+#define NVGPU_GM20B_REGOPS_GM20B_H
 
 struct dbg_session_gk20a;
 
@@ -41,4 +41,4 @@ const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void);
 u64 gm20b_get_qctl_whitelist_ranges_count(void);
 int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s);
 
-#endif /* __REGOPS_GM20B_H_ */
+#endif /* NVGPU_GM20B_REGOPS_GM20B_H */