From 5d85d2607d1da2765d82cdbdcda16e632cad7c80 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 30 Apr 2019 10:59:28 -0700 Subject: [PATCH] gpu: nvgpu: runlist MISRA fix for rule 2.2 Removed initialization of ret in tu104_runlist_wait_pending, as it is immediately overwritten with ret value from nvgpu_timeout_init. Jira NVGPU-3378 Change-Id: Icb565c173ba1ab7ad13ef7393888ab7832257d26 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2109478 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala Reviewed-by: Deepak Nibade Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.c b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.c index 90514c9f0..53c394520 100644 --- a/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.c +++ b/drivers/gpu/nvgpu/hal/fifo/runlist_fifo_tu104.c @@ -67,7 +67,7 @@ int tu104_runlist_wait_pending(struct gk20a *g, u32 runlist_id) { struct nvgpu_timeout timeout; u32 delay = POLL_DELAY_MIN_US; - int ret = -ETIMEDOUT; + int ret; ret = nvgpu_timeout_init(g, &timeout, nvgpu_get_poll_timeout(g), NVGPU_TIMER_CPU_TIMER);