diff --git a/userspace/required_tests.json b/userspace/required_tests.json index cc651b6e8..32c79fa8f 100644 --- a/userspace/required_tests.json +++ b/userspace/required_tests.json @@ -2009,6 +2009,12 @@ "unit": "nvgpu-pmu", "test_level": 0 }, + { + "test": "test_pmu_isr", + "case": "pmu_isr", + "unit": "nvgpu-pmu", + "test_level": 0 + }, { "test": "test_nvgpu_alloc_destroy", "case": "alloc_destroy", diff --git a/userspace/units/acr/nvgpu-acr.c b/userspace/units/acr/nvgpu-acr.c index 2dde112e2..aeff485b6 100644 --- a/userspace/units/acr/nvgpu-acr.c +++ b/userspace/units/acr/nvgpu-acr.c @@ -36,19 +36,19 @@ #include #include + #include #include #include #include #include #include +#include #include "nvgpu-acr.h" #include "../falcon/falcon_utf.h" #include "../gr/nvgpu-gr-gv11b.h" -struct utf_falcon *pmu_flcn, *gpccs_flcn; - #define NV_PMC_BOOT_0_ARCHITECTURE_GV110 (0x00000015 << \ NVGPU_GPU_ARCHITECTURE_SHIFT) #define NV_PMC_BOOT_0_IMPLEMENTATION_B 0xB @@ -59,6 +59,10 @@ struct utf_falcon *pmu_flcn, *gpccs_flcn; #define NV_PBB_FBHUB_REGSPACE 0x100B00 +#define BAR0_ERRORS_NUM 6 + +struct utf_falcon *pmu_flcn, *gpccs_flcn; + static int stub_gv11b_bar0_error_status(struct gk20a *g, u32 *bar0_status, u32 *etype) { @@ -198,7 +202,6 @@ static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g) unit_return_fail(m, "BAR1 is not supported on Volta+\n"); } - /* * Initialize utf & nvgpu falcon * for test usage @@ -207,6 +210,7 @@ static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g) if (pmu_flcn == NULL) { return -ENODEV; } + gpccs_flcn = nvgpu_utf_falcon_init(m, g, FALCON_ID_GPCCS); if (gpccs_flcn == NULL) { return -ENODEV; @@ -303,10 +307,18 @@ int test_acr_bootstrap_hs_acr(struct unit_module *m, struct gk20a *g, void *args) { - int err; + int err, i; struct nvgpu_reg_access access; struct nvgpu_posix_fault_inj *kmem_fi = nvgpu_kmem_get_fault_injection(); + u64 pmu_bar0_error[BAR0_ERRORS_NUM] = { + pwr_pmu_bar0_error_status_timeout_host_m(), + pwr_pmu_bar0_error_status_timeout_fecs_m(), + pwr_pmu_bar0_error_status_cmd_hwerr_m(), + pwr_pmu_bar0_error_status_fecserr_m(), + pwr_pmu_bar0_error_status_hosterr_m(), + 0xFF + }; /* * Initialise the test env @@ -316,6 +328,12 @@ int test_acr_bootstrap_hs_acr(struct unit_module *m, unit_return_fail(m, "Test env init failed\n"); } + if (nvgpu_posix_io_add_reg_space(g, + pwr_pmu_bar0_error_status_r(), 0x4) != 0) { + unit_err(m, "Add pwr_pmu_bar0_error_status reg space failed!\n"); + return -ENOMEM; + } + nvgpu_mutex_acquire(&g->tpc_pg_lock); /* @@ -412,9 +430,31 @@ int test_acr_bootstrap_hs_acr(struct unit_module *m, } /* - * Case 7: branch coverage + * Adding test cases to test gv11b_pmu_bar0_error_status() */ pmu_flcn->flcn->is_falcon_supported = true; + g->acr->acr.acr_engine_bus_err_status = g->ops.pmu.bar0_error_status; + for (i = 0; i < BAR0_ERRORS_NUM; i++) { + /* + * Write error values to the + * pwr_pmu_bar0_error_status_r() register + */ + nvgpu_posix_io_writel_reg_space(g, + pwr_pmu_bar0_error_status_r(), pmu_bar0_error[i]); + err = nvgpu_acr_bootstrap_hs_acr(g, g->acr); + + if (err != -EIO) { + unit_return_fail(m, "bar0_error_status error conditions" + "failed"); + } + } + + /* + * Case 7: branch coverage + */ + nvgpu_posix_io_writel_reg_space(g, + pwr_pmu_bar0_error_status_r(), 0); + g->acr->acr.acr_engine_bus_err_status = g->ops.pmu.bar0_error_status; g->acr->acr.acr_validate_mem_integrity = NULL; err = nvgpu_acr_bootstrap_hs_acr(g, g->acr); @@ -699,7 +739,7 @@ int test_acr_prepare_ucode_blob(struct unit_module *m, } /* - * case:pass scenario + * Case 3: pass scenario */ g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110; g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B; diff --git a/userspace/units/pmu/nvgpu-pmu.c b/userspace/units/pmu/nvgpu-pmu.c index 2803c108a..d47d5fc1f 100644 --- a/userspace/units/pmu/nvgpu-pmu.c +++ b/userspace/units/pmu/nvgpu-pmu.c @@ -30,10 +30,12 @@ #include #include #include +#include #include #include #include "hal/fuse/fuse_gm20b.h" +#include "hal/pmu/pmu_gk20a.h" #include "../falcon/falcon_utf.h" #include "../gr/nvgpu-gr-gv11b.h" @@ -488,6 +490,48 @@ static int test_pmu_reset(struct unit_module *m, return UNIT_SUCCESS; } +static int test_pmu_isr(struct unit_module *m, + struct gk20a *g, void *args) +{ int err; + struct nvgpu_pmu *pmu = g->pmu; + pmu->isr_enabled = true; + + /* + * initialize falcon + */ + if (init_pmu_falcon_test_env(m, g) != 0) { + unit_return_fail(m, "Module init failed\n"); + } + + err = g->ops.ecc.ecc_init_support(g); + if (err != 0) { + unit_return_fail(m, "ecc init failed\n"); + } + + /* + * initialize PMU + */ + err = nvgpu_pmu_early_init(g); + if (err != 0) { + unit_return_fail(m, "nvgpu_pmu_early_init failed\n"); + } + + /* + * Set the IRQ stat and mask registers + */ + nvgpu_posix_io_writel_reg_space(g, pwr_falcon_irqstat_r(), + pwr_falcon_irqstat_ext_ecc_parity_true_f()); + + nvgpu_posix_io_writel_reg_space(g, pwr_falcon_irqmask_r(), + pwr_falcon_irqstat_ext_ecc_parity_true_f()); + + nvgpu_posix_io_writel_reg_space(g, pwr_falcon_irqdest_r(), + pwr_falcon_irqstat_ext_ecc_parity_true_f()); + + g->ops.pmu.pmu_isr(g); + + return UNIT_SUCCESS; +} static int free_falcon_test_env(struct unit_module *m, struct gk20a *g, void *__args) { @@ -507,6 +551,7 @@ struct unit_module_test nvgpu_pmu_tests[] = { UNIT_TEST(pmu_early_init, test_pmu_early_init, NULL, 0), UNIT_TEST(pmu_remove_support, test_pmu_remove_support, NULL, 0), UNIT_TEST(pmu_reset, test_pmu_reset, NULL, 0), + UNIT_TEST(pmu_isr, test_pmu_isr, NULL, 0), UNIT_TEST(falcon_free_test_env, free_falcon_test_env, NULL, 0), };