From 5e9bdbc80de2af733ef5b62c0b7c7bb2b29dd3be Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Wed, 18 Dec 2019 17:49:22 -0500 Subject: [PATCH] gpu: nvgpu: runlist update timeout in safety Runlist update occurs in non-mission mode, when adding/removing channel/TSGs. The pending bit is a debug only feature. As a result logging a warning is sufficient. We expect other HW safety mechanisms such as PBDMA timeout to detect issues that caused pending to not clear. It's possible bad base address could cause some MMU faults too. Worst case we rely on the application level task monitor to detect the GPU tasks are not completing on time. Jira NVGPU-4322 Change-Id: I7233770349db5dfad6904170a1e9a2d5eada70b2 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2265094 Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-misra Reviewed-by: svc-mobile-cert Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/rc/rc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/nvgpu/common/rc/rc.c b/drivers/gpu/nvgpu/common/rc/rc.c index a3b95ce0e..218f2b60a 100644 --- a/drivers/gpu/nvgpu/common/rc/rc.c +++ b/drivers/gpu/nvgpu/common/rc/rc.c @@ -146,6 +146,19 @@ void nvgpu_rc_runlist_update(struct gk20a *g, u32 runlist_id) RC_TYPE_RUNLIST_UPDATE_TIMEOUT); } #else + /* + * Runlist update occurs in non-mission mode, when + * adding/removing channel/TSGs. The pending bit + * is a debug only feature. As a result logging a + * warning is sufficient. + * We expect other HW safety mechanisms such as + * PBDMA timeout to detect issues that caused pending + * to not clear. It's possible bad base address could + * cause some MMU faults too. + * Worst case we rely on the application level task + * monitor to detect the GPU tasks are not completing + * on time. + */ WARN_ON(!g->sw_quiesce_pending); #endif }