diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 755aa9221..9959a8220 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -82,6 +82,7 @@ ccflags-y += -DCONFIG_NVGPU_FALCON_NON_FUSA ccflags-y += -DCONFIG_NVGPU_IOCTL_NON_FUSA ccflags-y += -DCONFIG_NVGPU_NON_FUSA ccflags-y += -DCONFIG_NVGPU_INJECT_HWERR +ccflags-y += -DCONFIG_NVGPU_NONSTALL_INTR ccflags-y += -DCONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT ccflags-y += -DCONFIG_NVGPU_SET_FALCON_ACCESS_MAP ccflags-y += -DCONFIG_NVGPU_SW_SEMAPHORE diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs index e81464a6d..a28088f9c 100644 --- a/drivers/gpu/nvgpu/Makefile.shared.configs +++ b/drivers/gpu/nvgpu/Makefile.shared.configs @@ -316,6 +316,10 @@ ifeq ($(CONFIG_NVGPU_GSP_SCHEDULER),1) CONFIG_NVGPU_GSP_STRESS_TEST := 1 NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_GSP_STRESS_TEST endif +# Enable Nonstall interrupt support for normal build +CONFIG_NVGPU_NONSTALL_INTR := 1 +NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_NONSTALL_INTR + endif endif diff --git a/drivers/gpu/nvgpu/common/ce/ce.c b/drivers/gpu/nvgpu/common/ce/ce.c index 928fa4c8f..2258c81f9 100644 --- a/drivers/gpu/nvgpu/common/ce/ce.c +++ b/drivers/gpu/nvgpu/common/ce/ce.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -75,7 +75,9 @@ int nvgpu_ce_init_support(struct gk20a *g) /** Enable interrupts at MC level */ nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_CE, NVGPU_CIC_INTR_ENABLE); +#endif return 0; } diff --git a/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c b/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c index 49c7b07f9..d920b2539 100644 --- a/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c +++ b/drivers/gpu/nvgpu/common/cic/mon/mon_intr.c @@ -49,6 +49,7 @@ void nvgpu_cic_mon_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR void nvgpu_cic_mon_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable) { unsigned long flags = 0; @@ -57,6 +58,7 @@ void nvgpu_cic_mon_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool ena g->ops.mc.intr_nonstall_unit_config(g, unit, enable); nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); } +#endif void nvgpu_cic_mon_intr_stall_pause(struct gk20a *g) { @@ -76,6 +78,7 @@ void nvgpu_cic_mon_intr_stall_resume(struct gk20a *g) nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR void nvgpu_cic_mon_intr_nonstall_pause(struct gk20a *g) { unsigned long flags = 0; @@ -149,6 +152,7 @@ void nvgpu_cic_mon_intr_nonstall_handle(struct gk20a *g) (void)nvgpu_cic_rm_broadcast_last_irq_nonstall(g); } +#endif u32 nvgpu_cic_mon_intr_stall_isr(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/common/cic/rm/cic_rm_priv.h b/drivers/gpu/nvgpu/common/cic/rm/cic_rm_priv.h index 98067d4ac..d2a7d56a5 100644 --- a/drivers/gpu/nvgpu/common/cic/rm/cic_rm_priv.h +++ b/drivers/gpu/nvgpu/common/cic/rm/cic_rm_priv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -44,6 +44,7 @@ struct nvgpu_cic_rm { */ nvgpu_atomic_t sw_irq_stall_pending; +#ifdef CONFIG_NVGPU_NONSTALL_INTR /** * One of the condition variables needed to keep track of deferred * interrupts. @@ -59,6 +60,7 @@ struct nvgpu_cic_rm { * non-stalling interrupt handler and reset to 0 on exit. */ nvgpu_atomic_t sw_irq_nonstall_pending; +#endif }; #endif /* CIC_RM_PRIV_H */ diff --git a/drivers/gpu/nvgpu/common/cic/rm/rm_init.c b/drivers/gpu/nvgpu/common/cic/rm/rm_init.c index 74bf1b104..433517d77 100644 --- a/drivers/gpu/nvgpu/common/cic/rm/rm_init.c +++ b/drivers/gpu/nvgpu/common/cic/rm/rm_init.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -66,16 +66,20 @@ int nvgpu_cic_rm_init_vars(struct gk20a *g) goto cleanup; } +#ifdef CONFIG_NVGPU_NONSTALL_INTR err = nvgpu_cond_init(&cic_rm->sw_irq_nonstall_last_handled_cond); if (err != 0) { nvgpu_err(g, "sw irq nonstall cond init failed\n"); goto cleanup_cond; } +#endif return 0; +#ifdef CONFIG_NVGPU_NONSTALL_INTR cleanup_cond: nvgpu_cond_destroy(&cic_rm->sw_irq_stall_last_handled_cond); +#endif cleanup: return err; } @@ -92,7 +96,9 @@ int nvgpu_cic_rm_deinit_vars(struct gk20a *g) } nvgpu_cond_destroy(&cic_rm->sw_irq_stall_last_handled_cond); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cond_destroy(&cic_rm->sw_irq_nonstall_last_handled_cond); +#endif return 0; } diff --git a/drivers/gpu/nvgpu/common/cic/rm/rm_intr.c b/drivers/gpu/nvgpu/common/cic/rm/rm_intr.c index 4ec4f708c..b01b37c9c 100644 --- a/drivers/gpu/nvgpu/common/cic/rm/rm_intr.c +++ b/drivers/gpu/nvgpu/common/cic/rm/rm_intr.c @@ -30,10 +30,12 @@ void nvgpu_cic_rm_set_irq_stall(struct gk20a *g, u32 value) nvgpu_atomic_set(&g->cic_rm->sw_irq_stall_pending, (int)value); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR void nvgpu_cic_rm_set_irq_nonstall(struct gk20a *g, u32 value) { nvgpu_atomic_set(&g->cic_rm->sw_irq_nonstall_pending, (int)value); } +#endif int nvgpu_cic_rm_broadcast_last_irq_stall(struct gk20a *g) { @@ -50,6 +52,7 @@ int nvgpu_cic_rm_broadcast_last_irq_stall(struct gk20a *g) return err; } +#ifdef CONFIG_NVGPU_NONSTALL_INTR int nvgpu_cic_rm_broadcast_last_irq_nonstall(struct gk20a *g) { int err = 0; @@ -64,6 +67,7 @@ int nvgpu_cic_rm_broadcast_last_irq_nonstall(struct gk20a *g) return err; } +#endif int nvgpu_cic_rm_wait_for_stall_interrupts(struct gk20a *g, u32 timeout) { @@ -73,6 +77,7 @@ int nvgpu_cic_rm_wait_for_stall_interrupts(struct gk20a *g, u32 timeout) timeout); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR int nvgpu_cic_rm_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout) { /* wait until all non-stalling irqs are handled */ @@ -80,6 +85,7 @@ int nvgpu_cic_rm_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout) nvgpu_atomic_read(&g->cic_rm->sw_irq_nonstall_pending) == 0, timeout); } +#endif void nvgpu_cic_rm_wait_for_deferred_interrupts(struct gk20a *g) { @@ -90,10 +96,12 @@ void nvgpu_cic_rm_wait_for_deferred_interrupts(struct gk20a *g) nvgpu_err(g, "wait for stall interrupts failed %d", ret); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR ret = nvgpu_cic_rm_wait_for_nonstall_interrupts(g, 0U); if (ret != 0) { nvgpu_err(g, "wait for nonstall interrupts failed %d", ret); } +#endif } #ifdef CONFIG_NVGPU_NON_FUSA diff --git a/drivers/gpu/nvgpu/common/fifo/fifo.c b/drivers/gpu/nvgpu/common/fifo/fifo.c index 36cd0ca82..017625c75 100644 --- a/drivers/gpu/nvgpu/common/fifo/fifo.c +++ b/drivers/gpu/nvgpu/common/fifo/fifo.c @@ -1,7 +1,7 @@ /* * FIFO * - * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -283,8 +283,10 @@ static void disable_fifo_interrupts(struct gk20a *g) if (g->ops.fifo.intr_top_enable == NULL) { nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_DISABLE); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_DISABLE); +#endif } else { g->ops.fifo.intr_top_enable(g, NVGPU_CIC_INTR_DISABLE); } diff --git a/drivers/gpu/nvgpu/common/gr/gr.c b/drivers/gpu/nvgpu/common/gr/gr.c index c8ec5fef1..94b57b5cf 100644 --- a/drivers/gpu/nvgpu/common/gr/gr.c +++ b/drivers/gpu/nvgpu/common/gr/gr.c @@ -190,8 +190,10 @@ static void disable_gr_interrupts(struct gk20a *g) /** Disable interrupts at MC level */ nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_DISABLE); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_DISABLE); +#endif } int nvgpu_gr_suspend(struct gk20a *g) @@ -599,7 +601,9 @@ static int gr_init_prepare_hw(struct gk20a *g) /** Enable interrupts at MC level */ nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE); +#endif return nvgpu_gr_exec_with_ret_for_each_instance(g, gr_init_prepare_hw_impl(g)); @@ -713,7 +717,9 @@ static int nvgpu_gr_enable_hw_for_instance(struct gk20a *g) /** Enable interrupts at MC level */ nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_GR, NVGPU_CIC_INTR_ENABLE); +#endif err = gr_init_prepare_hw_impl(g); if (err != 0) { diff --git a/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c index 919d5cb05..fe275e05d 100644 --- a/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/bus/bus_gk20a_fusa.c @@ -39,7 +39,9 @@ int gk20a_bus_init_hw(struct gk20a *g) { u32 intr_en_mask = 0U; +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, NVGPU_CIC_INTR_ENABLE); +#endif /* * Note: bus_intr_en_0 is for routing intr to stall tree (mc_intr_0) diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c index b396ba83b..c51fdfa70 100644 --- a/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/fifo_gv11b_fusa.c @@ -1,7 +1,7 @@ /* * GV11B fifo * - * Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -40,8 +40,10 @@ static void enable_fifo_interrupts(struct gk20a *g) { nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_ENABLE); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_ENABLE); +#endif g->ops.fifo.intr_0_enable(g, true); g->ops.fifo.intr_1_enable(g, true); diff --git a/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h b/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h index 7dd780ef8..0c26ab534 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/cic_mon.h @@ -426,6 +426,7 @@ u32 nvgpu_cic_mon_intr_stall_isr(struct gk20a *g); */ void nvgpu_cic_mon_intr_stall_handle(struct gk20a *g); +#ifdef CONFIG_NVGPU_NONSTALL_INTR /** * @brief Top half of nonstall interrupt ISR. * @@ -452,6 +453,7 @@ u32 nvgpu_cic_mon_intr_nonstall_isr(struct gk20a *g); * nonstall operations. */ void nvgpu_cic_mon_intr_nonstall_handle(struct gk20a *g); +#endif /** * @brief Clear the GPU device interrupts at master level. @@ -516,6 +518,7 @@ void nvgpu_cic_mon_intr_mask(struct gk20a *g); */ void nvgpu_cic_mon_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable); +#ifdef CONFIG_NVGPU_NONSTALL_INTR /** * @brief Enable/Disable the non-stalling interrupts for given GPU unit at the * master level. @@ -557,6 +560,7 @@ void nvgpu_cic_mon_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable * - Release the spinlock g->mc.intr_lock. */ void nvgpu_cic_mon_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable); +#endif /** * @brief Disable/Pause the stalling interrupts. @@ -591,6 +595,7 @@ void nvgpu_cic_mon_intr_stall_pause(struct gk20a *g); */ void nvgpu_cic_mon_intr_stall_resume(struct gk20a *g); +#ifdef CONFIG_NVGPU_NONSTALL_INTR /** * @brief Disable/Pause the non-stalling interrupts. * @@ -625,6 +630,7 @@ void nvgpu_cic_mon_intr_nonstall_pause(struct gk20a *g); * - Release the spinlock g->mc.intr_lock. */ void nvgpu_cic_mon_intr_nonstall_resume(struct gk20a *g); +#endif void nvgpu_cic_mon_intr_enable(struct gk20a *g); diff --git a/libs/dgpu/libnvgpu-drv-dgpu_safe.export b/libs/dgpu/libnvgpu-drv-dgpu_safe.export index d10170f25..889c8255f 100644 --- a/libs/dgpu/libnvgpu-drv-dgpu_safe.export +++ b/libs/dgpu/libnvgpu-drv-dgpu_safe.export @@ -530,9 +530,6 @@ nvgpu_ltc_remove_support nvgpu_local_golden_image_get_fault_injection nvgpu_log_msg_impl nvgpu_cic_mon_intr_mask -nvgpu_cic_mon_intr_nonstall_pause -nvgpu_cic_mon_intr_nonstall_resume -nvgpu_cic_mon_intr_nonstall_unit_config nvgpu_cic_mon_intr_stall_pause nvgpu_cic_mon_intr_stall_resume nvgpu_cic_mon_intr_stall_unit_config diff --git a/libs/igpu/libnvgpu-drv-igpu_safe.export b/libs/igpu/libnvgpu-drv-igpu_safe.export index 94b407874..0b7c7e91d 100644 --- a/libs/igpu/libnvgpu-drv-igpu_safe.export +++ b/libs/igpu/libnvgpu-drv-igpu_safe.export @@ -547,9 +547,6 @@ nvgpu_ltc_remove_support nvgpu_local_golden_image_get_fault_injection nvgpu_log_msg_impl nvgpu_cic_mon_intr_mask -nvgpu_cic_mon_intr_nonstall_pause -nvgpu_cic_mon_intr_nonstall_resume -nvgpu_cic_mon_intr_nonstall_unit_config nvgpu_cic_mon_intr_stall_pause nvgpu_cic_mon_intr_stall_resume nvgpu_cic_mon_intr_stall_unit_config diff --git a/userspace/units/mc/nvgpu-mc.c b/userspace/units/mc/nvgpu-mc.c index 3fe279ab4..df638c77b 100644 --- a/userspace/units/mc/nvgpu-mc.c +++ b/userspace/units/mc/nvgpu-mc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -329,7 +329,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args) unit_return_fail(m, "failed to disable stall intr for unit %u val=0x%08x\n", unit, val); } - +#ifdef CONFIG_NVGPU_NONSTALL_INTR /* enable nonstall intr */ nvgpu_cic_mon_intr_nonstall_unit_config(g, unit, true); val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG); @@ -345,6 +345,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args) unit_return_fail(m, "failed to disable nonstall intr for unit %u val=0x%08x\n", unit, val); } +#endif } for (i = 0; i < ARRAY_SIZE(invalid_units); i++) { @@ -366,6 +367,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args) val); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR /* negative testing - invalid unit enable set - nonstall */ nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_REG, 0x0); /* clear en reg */ nvgpu_cic_mon_intr_nonstall_unit_config(g, invalid_units[i], true); @@ -383,6 +385,7 @@ int test_unit_config(struct unit_module *m, struct gk20a *g, void *args) unit_return_fail(m, "Incorrectly enabled non-stall interrupt for invalid unit, val=0x%08x\n", val); } +#endif } return UNIT_SUCCESS; @@ -392,7 +395,9 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args) { u32 val; u32 expected_stall_val = mc_intr_priv_ring_pending_f(); +#ifdef CONFIG_NVGPU_NONSTALL_INTR u32 expected_nonstall_val = mc_intr_pbus_pending_f(); +#endif void (*save_func)(struct gk20a *g); /* clear regs */ @@ -410,7 +415,9 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args) /* enable something to pause and resume */ nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_PRIV_RING, true); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_BUS, true); +#endif /* pause stall */ nvgpu_cic_mon_intr_stall_pause(g); @@ -419,12 +426,14 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args) unit_return_fail(m, "failed to pause stall intr\n"); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR /* pause nonstall */ nvgpu_cic_mon_intr_nonstall_pause(g); val = nvgpu_posix_io_readl_reg_space(g, NONSTALL_EN_REG); if (val != 0) { unit_return_fail(m, "failed to pause nonstall intr\n"); } +#endif /* resume stall */ nvgpu_posix_io_writel_reg_space(g, STALL_EN_SET_REG, 0x0); @@ -434,6 +443,7 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args) unit_return_fail(m, "failed to resume stall intr\n"); } +#ifdef CONFIG_NVGPU_NONSTALL_INTR /* resume nonstall */ nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_SET_REG, 0x0); nvgpu_cic_mon_intr_nonstall_resume(g); @@ -441,10 +451,13 @@ int test_pause_resume_mask(struct unit_module *m, struct gk20a *g, void *args) if (val != expected_nonstall_val) { unit_return_fail(m, "failed to resume nonstall intr\n"); } +#endif /* clear regs */ nvgpu_posix_io_writel_reg_space(g, STALL_EN_CLEAR_REG, 0x0); +#ifdef CONFIG_NVGPU_NONSTALL_INTR nvgpu_posix_io_writel_reg_space(g, NONSTALL_EN_CLEAR_REG, 0x0); +#endif /* mask all */ nvgpu_cic_mon_intr_mask(g);