From 5ecd220d3292f1dd2ef1760c21118dd89b7f1537 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 13 Jul 2017 00:40:31 +0100 Subject: [PATCH] gpu: nvgpu: Add su_rd_coalesce register field Add the surface rd coalesce field in the register that controls read coalescing. Bug 200314091 Change-Id: I185ad7e6ef64ecae9369e26d22a7381611ddc693 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1518305 (cherry picked from commit 0dd02e634ddc2f3e048b39048d2299d24401fdf8) Reviewed-on: https://git-master.nvidia.com/r/1551738 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Darren Sun Tested-by: Darren Sun Reviewed-by: Hayden Du --- drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index bc966416f..5721ff420 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h @@ -2266,6 +2266,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) { return 0x1 << 2; } +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) +{ + return 0x1 << 4; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h index a8ca9b8da..922b213ca 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h @@ -2550,6 +2550,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) { return 0x1 << 2; } +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) +{ + return 0x1 << 4; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac;