diff --git a/Makefile.umbrella.tmk b/Makefile.umbrella.tmk
index 220549a59..a2e383c21 100644
--- a/Makefile.umbrella.tmk
+++ b/Makefile.umbrella.tmk
@@ -49,7 +49,6 @@ NV_REPOSITORY_COMPONENTS += libs/dgpu
 NV_REPOSITORY_COMPONENTS += userspace
 NV_REPOSITORY_COMPONENTS += userspace/units/posix/bitops
 NV_REPOSITORY_COMPONENTS += userspace/units/posix/env
-NV_REPOSITORY_COMPONENTS += userspace/units/posix/mockio
 NV_REPOSITORY_COMPONENTS += userspace/units/posix/fault-injection
 NV_REPOSITORY_COMPONENTS += userspace/units/posix/bug
 NV_REPOSITORY_COMPONENTS += userspace/units/posix/os_sched
@@ -163,7 +162,6 @@ NV_REPOSITORY_COMPONENTS += userspace/units/ce
 NV_REPOSITORY_COMPONENTS += userspace/units/cg
 NV_REPOSITORY_COMPONENTS += userspace/units/rc
 NV_REPOSITORY_COMPONENTS += userspace/units/sync
-NV_REPOSITORY_COMPONENTS += userspace/units/mock-iospace
 NV_REPOSITORY_COMPONENTS += userspace/units/ecc
 NV_REPOSITORY_COMPONENTS += userspace/units/io
 endif
diff --git a/arch/nvgpu-posix.yaml b/arch/nvgpu-posix.yaml
index c6b48bf8b..887da4e9b 100644
--- a/arch/nvgpu-posix.yaml
+++ b/arch/nvgpu-posix.yaml
@@ -34,7 +34,8 @@ all:
              os/posix/posix-vidmem.c,
              os/posix/fecs_trace_posix.c,
              os/posix/stubs.c,
-             os/posix/posix-vpr.c ]
+             os/posix/posix-vpr.c,
+             os/posix/mock-registers.c ]
 
 headers:
   safe: no
@@ -42,6 +43,7 @@ headers:
   sources: [ include/nvgpu/posix/barrier.h,
              include/nvgpu/posix/dma.h,
              include/nvgpu/posix/io.h,
+             include/nvgpu/posix/mock-regs.h,
              include/nvgpu/posix/log.h,
              include/nvgpu/posix/nvgpu_mem.h,
              include/nvgpu/posix/pci.h,
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index 47864c74b..7f4e1c7ee 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -25,6 +25,7 @@ srcs :=
 ifdef NVGPU_POSIX
 srcs +=	os/posix/nvgpu.c \
 	os/posix/posix-io.c \
+	os/posix/mock-registers.c \
 	os/posix/posix-nvgpu_mem.c \
 	os/posix/posix-dma.c \
 	os/posix/posix-vm.c \
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/mock-regs.h b/drivers/gpu/nvgpu/include/nvgpu/posix/mock-regs.h
new file mode 100644
index 000000000..8f2f0ac76
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/mock-regs.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property and
+ * proprietary rights in and to this software and related documentation.  Any
+ * use, reproduction, disclosure or distribution of this software and related
+ * documentation without an express license agreement from NVIDIA Corporation
+ * is strictly prohibited.
+ */
+
+#ifndef NVGPU_POSIX_MOCK_REGS_H
+#define NVGPU_POSIX_MOCK_REGS_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+struct nvgpu_mock_iospace {
+	u32             base;
+	size_t          size;
+	const uint32_t *data;
+};
+
+#define MOCK_REGS_GR		0U
+#define MOCK_REGS_FUSE		1U
+#define MOCK_REGS_MASTER	2U
+#define MOCK_REGS_TOP		3U
+#define MOCK_REGS_FIFO		4U
+#define MOCK_REGS_PRI		5U
+#define MOCK_REGS_PBDMA		6U
+#define MOCK_REGS_CCSR		7U
+#define MOCK_REGS_USERMODE	8U
+#define MOCK_REGS_CE		9U
+#define MOCK_REGS_PBUS		10U
+#define MOCK_REGS_HSHUB		11U
+#define MOCK_REGS_FB		12U
+#define MOCK_REGS_LAST		13U
+
+/**
+ * Load a mocked register list into the passed IO space description.
+ */
+int nvgpu_get_mock_reglist(struct gk20a *g, u32 reg_space,
+			   struct nvgpu_mock_iospace *iospace);
+
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h b/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
index c9e2cd1bd..0b823fe6a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,17 @@
 #ifndef NVGPU_POSIX_PROBE_H
 #define NVGPU_POSIX_PROBE_H
 
+/*
+ * In the unit test FW the POSIX code is expecting a gv11b at the moment.
+ */
+#define NV_PMC_BOOT_0_ARCHITECTURE_GV110	(0x00000015 << \
+						NVGPU_GPU_ARCHITECTURE_SHIFT)
+#define NV_PMC_BOOT_0_IMPLEMENTATION_B		0xB
+
+#define NV_PMC_BOOT_0_ARCHITECTURE_INVALID	(0x00000018 << \
+						NVGPU_GPU_ARCHITECTURE_SHIFT)
+#define NV_PMC_BOOT_0_IMPLEMENTATION_INVALID	0xD
+
 struct gk20a;
 
 struct gk20a *nvgpu_posix_probe(void);
diff --git a/drivers/gpu/nvgpu/os/posix/fuse.c b/drivers/gpu/nvgpu/os/posix/fuse.c
index 91fd88cc4..cab09f6ef 100644
--- a/drivers/gpu/nvgpu/os/posix/fuse.c
+++ b/drivers/gpu/nvgpu/os/posix/fuse.c
@@ -26,6 +26,8 @@
 #include <nvgpu/posix/io.h>
 #include <nvgpu/posix/soc_fuse.h>
 
+#include "hal/fuse/fuse_gm20b.h"
+
 #ifdef CONFIG_NVGPU_NON_FUSA
 int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id)
 {
@@ -87,6 +89,14 @@ int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
 	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
 
 	if (p->callbacks == NULL || p->callbacks->tegra_fuse_readl == NULL) {
+		/*
+		 * Generally for nvgpu, if priv_sec is enabled, we are expecting
+		 * WPR to be enabled and auto fetching of VPR to _not_ be
+		 * disabled (in other words VPR autofetch to be enabled - cause
+		 * that's not confusing at all).
+		 */
+		*val = GCPLEX_CONFIG_WPR_ENABLED_MASK;
+
 		return 0;
 	}
 
diff --git a/userspace/units/mock-iospace/gv11b_mock_regs.c b/drivers/gpu/nvgpu/os/posix/mock-registers.c
similarity index 99%
rename from userspace/units/mock-iospace/gv11b_mock_regs.c
rename to drivers/gpu/nvgpu/os/posix/mock-registers.c
index 609f48b47..588ec5679 100644
--- a/userspace/units/mock-iospace/gv11b_mock_regs.c
+++ b/drivers/gpu/nvgpu/os/posix/mock-registers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,14 +19,18 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
-#include <inttypes.h>
-#include <stddef.h>
-#include <stdint.h>
-#include <errno.h>
 
-#include "include/gv11b_mock_regs.h"
+#include <nvgpu/types.h>
 
-static const uint32_t gv11b_gr_regs[] = {
+#include <nvgpu/posix/mock-regs.h>
+
+/*
+ * We use this to get usermode_cfg0_r() - necessary for the base address
+ * of the usermode region.
+ */
+#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
+
+static const uint32_t nvgpu_gv11b_gr_regs[] = {
 /* 0x17400000 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 /* 0x17400010 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 /* 0x17400020 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
@@ -131101,7 +131105,7 @@ static const uint32_t gv11b_gr_regs[] = {
 /* 0x175ffff0 */ 0xbadf1100, 0xbadf1100, 0xbadf1100, 0xbadf1100,
 };
 
-static const uint32_t gv11b_fuse_regs[] = {
+static const uint32_t nvgpu_gv11b_fuse_regs[] = {
 /* 0x00021000 */ 0x000000ff, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 /* 0x00021010 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 /* 0x00021020 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
@@ -131360,7 +131364,7 @@ static const uint32_t gv11b_fuse_regs[] = {
 /* 0x00021ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 };
 
-static const uint32_t gv11b_master_regs[] = {
+static const uint32_t nvgpu_gv11b_master_regs[] = {
 /* 0x00000000 */ 0x15b000a1, 0x00000000, 0x00000000, 0xbadf5040,
 /* 0x00000010 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 /* 0x00000020 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
@@ -131619,7 +131623,7 @@ static const uint32_t gv11b_master_regs[] = {
 /* 0x00000ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 };
 
-static const uint32_t gv11b_top_regs[] = {
+static const uint32_t nvgpu_gv11b_top_regs[] = {
 /* 0x00022400 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
 /* 0x00022410 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0x00000081,
 /* 0x00022420 */ 0x04444924, 0x00000010, 0xbadf5040, 0xbadf5040,
@@ -131686,7 +131690,7 @@ static const uint32_t gv11b_top_regs[] = {
 /* 0x000227f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 };
 
-static const uint32_t gv11b_fifo_regs[] = {
+static const uint32_t nvgpu_gv11b_fifo_regs[] = {
 /* 0x00002000 */ 0x00000000, 0x00200003, 0x00000200, 0x0000c36f,
 /* 0x00002010 */ 0x0000000f, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 /* 0x00002020 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
@@ -132201,7 +132205,7 @@ static const uint32_t gv11b_fifo_regs[] = {
 /* 0x00003ff0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 };
 
-static const uint32_t gv11b_pri_regs[] = {
+static const uint32_t nvgpu_gv11b_pri_regs[] = {
 /* 0x00120000 */ 0x1b6536ca, 0x006536ca, 0x00000000, 0x00000000,
 /* 0x00120010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 /* 0x00120020 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
@@ -132268,7 +132272,7 @@ static const uint32_t gv11b_pri_regs[] = {
 /* 0x001203f0 */ 0xbadf5040, 0xbadf5040, 0xbadf5040, 0xbadf5040,
 };
 
-static const uint32_t gv11b_pbdma_regs[] = {
+static const uint32_t nvgpu_gv11b_pbdma_regs[] = {
 /* 0x00040000 */ 0x00000003, 0x00000000, 0x1cd05e03, 0x00000008,
 /* 0x00040010 */ 0x0000c36f, 0x00000003, 0x00408050, 0x0000001f,
 /* 0x00040020 */ 0x00408050, 0x8000001f, 0x00000000, 0x003c3134,
@@ -140463,7 +140467,7 @@ static const uint32_t gv11b_pbdma_regs[] = {
 /* 0x0005fff0 */ 0xbad00100, 0xbad00100, 0xbad00100, 0xbad00100,
 };
 
-static const uint32_t gv11b_ccsr_regs[] = {
+static const uint32_t nvgpu_gv11b_ccsr_regs[] = {
 /* 0x00800000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 /* 0x00800010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 /* 0x00800020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -144562,43 +144566,77 @@ static const uint32_t gv11b_ccsr_regs[] = {
 /* 0x0080fff0 */ 0xbad00100, 0xbad00100, 0xbad00100, 0xbad00100,
 };
 
-int gv11b_get_mock_iospace(int reg_idx, struct mock_iospace *iospace)
+int nvgpu_get_mock_reglist(struct gk20a *g, u32 reg_idx,
+			   struct nvgpu_mock_iospace *iospace)
 {
 	switch (reg_idx) {
-		case gv11b_gr_reg_idx:
-			iospace->data = gv11b_gr_regs;
-			iospace->size = sizeof(gv11b_gr_regs);
-			break;
-		case gv11b_fuse_reg_idx:
-			iospace->data = gv11b_fuse_regs;
-			iospace->size = sizeof(gv11b_fuse_regs);
-			break;
-		case gv11b_master_reg_idx:
-			iospace->data = gv11b_master_regs;
-			iospace->size = sizeof(gv11b_master_regs);
-			break;
-		case gv11b_top_reg_idx:
-			iospace->data = gv11b_top_regs;
-			iospace->size = sizeof(gv11b_top_regs);
-			break;
-		case gv11b_fifo_reg_idx:
-			iospace->data  = gv11b_fifo_regs;
-			iospace->size = sizeof(gv11b_fifo_regs);
-			break;
-		case gv11b_pri_reg_idx:
-			iospace->data = gv11b_pri_regs;
-			iospace->size = sizeof(gv11b_pri_regs);
-			break;
-		case gv11b_pbdma_reg_idx:
-			iospace->data = gv11b_pbdma_regs;
-			iospace->size = sizeof(gv11b_pbdma_regs);
-			break;
-		case gv11b_ccsr_reg_idx:
-			iospace->data = gv11b_ccsr_regs;
-			iospace->size = sizeof(gv11b_ccsr_regs);
-			break;
-		default:
-			return -EINVAL;
+	case MOCK_REGS_GR:
+		iospace->data = nvgpu_gv11b_gr_regs;
+		iospace->size = sizeof(nvgpu_gv11b_gr_regs);
+		iospace->base = 0x400000;
+		break;
+	case MOCK_REGS_FUSE:
+		iospace->data = nvgpu_gv11b_fuse_regs;
+		iospace->size = sizeof(nvgpu_gv11b_fuse_regs);
+		iospace->base = 0x21000;
+		break;
+	case MOCK_REGS_MASTER:
+		iospace->data = nvgpu_gv11b_master_regs;
+		iospace->size = sizeof(nvgpu_gv11b_master_regs);
+		iospace->base = 0x0;
+		break;
+	case MOCK_REGS_TOP:
+		iospace->data = nvgpu_gv11b_top_regs;
+		iospace->size = sizeof(nvgpu_gv11b_top_regs);
+		iospace->base = 0x22400;
+		break;
+	case MOCK_REGS_FIFO:
+		iospace->data = nvgpu_gv11b_fifo_regs;
+		iospace->size = sizeof(nvgpu_gv11b_fifo_regs);
+		iospace->base = 0x2000;
+		break;
+	case MOCK_REGS_PRI:
+		iospace->data = nvgpu_gv11b_pri_regs;
+		iospace->size = sizeof(nvgpu_gv11b_pri_regs);
+		iospace->base = 0x120000;
+		break;
+	case MOCK_REGS_PBDMA:
+		iospace->data = nvgpu_gv11b_pbdma_regs;
+		iospace->size = sizeof(nvgpu_gv11b_pbdma_regs);
+		iospace->base = 0x40000;
+		break;
+	case MOCK_REGS_CCSR:
+		iospace->data = nvgpu_gv11b_ccsr_regs;
+		iospace->size = sizeof(nvgpu_gv11b_ccsr_regs);
+		iospace->base = 0x800000;
+		break;
+	case MOCK_REGS_USERMODE:
+		iospace->base = usermode_cfg0_r();
+		iospace->size = 0x10000;
+		iospace->data = NULL;
+		break;
+	case MOCK_REGS_CE:
+		iospace->base = 0x104000;
+		iospace->size = 0x2000;
+		iospace->data = NULL;
+		break;
+	case MOCK_REGS_PBUS:
+		iospace->base = 0x1000;
+		iospace->size = 0x1000;
+		iospace->data = NULL;
+		break;
+	case MOCK_REGS_HSHUB:
+		iospace->base = 0x1fbc00;
+		iospace->size = 0x400;
+		iospace->data = NULL;
+		break;
+	case MOCK_REGS_FB:
+		iospace->base = 0x100000;
+		iospace->size = 0x1000;
+		iospace->data = NULL;
+		break;
+	default:
+		return -EINVAL;
 	}
 
 	return 0;
diff --git a/drivers/gpu/nvgpu/os/posix/nvgpu.c b/drivers/gpu/nvgpu/os/posix/nvgpu.c
index d5a4f8ade..83992d216 100644
--- a/drivers/gpu/nvgpu/os/posix/nvgpu.c
+++ b/drivers/gpu/nvgpu/os/posix/nvgpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -29,11 +29,14 @@
 #include <nvgpu/atomic.h>
 #include <nvgpu/nvgpu_common.h>
 #include <nvgpu/nvgpu_init.h>
+#include <nvgpu/hal_init.h>
 #include <nvgpu/os_sched.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/enabled.h>
 
 #include <nvgpu/posix/probe.h>
+#include <nvgpu/posix/mock-regs.h>
+#include <nvgpu/posix/io.h>
 
 #include "os_posix.h"
 
@@ -51,6 +54,37 @@ struct nvgpu_posix_fault_inj *nvgpu_nvgpu_get_fault_injection(void)
 }
 #endif
 
+/*
+ * Write callback. Forward the write access to the mock IO framework.
+ */
+static void writel_access_reg_fn(struct gk20a *g,
+				 struct nvgpu_reg_access *access)
+{
+	nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
+}
+
+/*
+ * Read callback. Get the register value from the mock IO framework.
+ */
+static void readl_access_reg_fn(struct gk20a *g,
+				struct nvgpu_reg_access *access)
+{
+	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
+}
+
+static struct nvgpu_posix_io_callbacks default_posix_reg_callbacks = {
+	/* Write APIs all can use the same accessor. */
+	.writel          = writel_access_reg_fn,
+	.writel_check    = writel_access_reg_fn,
+	.bar1_writel     = writel_access_reg_fn,
+	.usermode_writel = writel_access_reg_fn,
+
+	/* Likewise for the read APIs. */
+	.__readl         = readl_access_reg_fn,
+	.readl           = readl_access_reg_fn,
+	.bar1_readl      = readl_access_reg_fn,
+};
+
 /*
  * Somewhat meaningless in userspace...
  */
@@ -160,6 +194,32 @@ void gk20a_idle(struct gk20a *g)
 	nvgpu_atomic_dec(&g->usage_count);
 }
 
+static void nvgpu_posix_load_regs(struct gk20a *g)
+{
+	u32 i;
+	int err;
+	struct nvgpu_mock_iospace space;
+	struct nvgpu_posix_io_reg_space *regs;
+
+	for (i = 0; i < MOCK_REGS_LAST; i++) {
+		err = nvgpu_get_mock_reglist(g, i, &space);
+		if (err) {
+			nvgpu_err(g, "Unknown IO regspace: %d; ignoring.", i);
+			continue;
+		}
+
+		err = nvgpu_posix_io_add_reg_space(g, space.base, space.size);
+		nvgpu_assert(err == 0);
+
+		regs = nvgpu_posix_io_get_reg_space(g, space.base);
+		nvgpu_assert(regs != NULL);
+
+		if (space.data != NULL) {
+			memcpy(regs->data, space.data, space.size);
+		}
+	}
+}
+
 /*
  * This function aims to initialize enough stuff to make unit testing worth
  * while. There are several interfaces and APIs that rely on the struct gk20a's
@@ -201,6 +261,29 @@ struct gk20a *nvgpu_posix_probe(void)
 		goto fail_enabled_flags;
 	}
 
+	/*
+	 * Initialize a bunch of gv11b register values.
+	 */
+	nvgpu_posix_io_init_reg_space(g);
+	nvgpu_posix_load_regs(g);
+
+	/*
+	 * Set up some default register IO callbacks that basically all
+	 * unit tests will be OK with. Unit tests that wish to override this
+	 * may do so.
+	 *
+	 * This needs to happen before the nvgpu_detect_chip() call below
+	 * otherise we bug out when trying to do a register read.
+	 */
+	(void)nvgpu_posix_register_io(g, &default_posix_reg_callbacks);
+
+	/*
+	 * Detect chip based on the regs we filled above. Most unit tests
+	 * will be fine with this; a few may have to undo a little bit of it
+	 * in roder to fully test the nvgpu_detect_chip() function.
+	 */
+	nvgpu_assert(nvgpu_detect_chip(g) == 0);
+
 	return g;
 
 fail_enabled_flags:
diff --git a/drivers/gpu/nvgpu/os/posix/posix-io.c b/drivers/gpu/nvgpu/os/posix/posix-io.c
index 9e16703ab..ce05b9e7b 100644
--- a/drivers/gpu/nvgpu/os/posix/posix-io.c
+++ b/drivers/gpu/nvgpu/os/posix/posix-io.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -231,7 +231,12 @@ int nvgpu_posix_io_register_reg_space(struct gk20a *g,
 		return -ENOMEM;
 	}
 
-	nvgpu_list_add_tail(&reg_space->link, &p->reg_space_head);
+	/*
+	 * Add new register spaces to the front of the list. This lets unit
+	 * tests define their own smaller register spaces that take precedence
+	 * over the default reg lists.
+	 */
+	nvgpu_list_add(&reg_space->link, &p->reg_space_head);
 	return 0;
 }
 
@@ -259,7 +264,7 @@ int nvgpu_posix_io_add_reg_space(struct gk20a *g, u32 base, u32 size)
 
 	new_reg_space->data = nvgpu_vzalloc(g, size);
 	if (new_reg_space->data == NULL) {
-		nvgpu_vfree(g, new_reg_space);
+		nvgpu_kfree(g, new_reg_space);
 		return -ENOMEM;
 	}
 
diff --git a/userspace/Makefile b/userspace/Makefile
index aadb38dfc..6a78f2224 100644
--- a/userspace/Makefile
+++ b/userspace/Makefile
@@ -54,7 +54,6 @@ INCLUDES= 				\
 	-I$(TWD)/../include		\
 	-I$(TWD)/../include/uapi	\
 	-I$(TWD)/include		\
-	-I$(UNIT_SRC)/mock-iospace/include
 
 # This is safety build by default.
 NV_BUILD_CONFIGURATION_IS_SAFETY=1
diff --git a/userspace/Makefile.sources b/userspace/Makefile.sources
index 2943d4e56..23ffdc33b 100644
--- a/userspace/Makefile.sources
+++ b/userspace/Makefile.sources
@@ -46,7 +46,6 @@ CORE_HEADERS :=	\
 UNITS :=				\
 	$(UNIT_SRC)/posix/env		\
 	$(UNIT_SRC)/posix/bitops	\
-	$(UNIT_SRC)/posix/mockio	\
 	$(UNIT_SRC)/posix/fault-injection \
 	$(UNIT_SRC)/posix/bug		\
 	$(UNIT_SRC)/posix/os_sched	\
@@ -102,7 +101,6 @@ UNITS :=				\
 	$(UNIT_SRC)/netlist		\
         $(UNIT_SRC)/fb 	        	\
 	$(UNIT_SRC)/fbp			\
-	$(UNIT_SRC)/mock-iospace	\
 	$(UNIT_SRC)/fifo		\
 	$(UNIT_SRC)/fifo/fifo/gk20a	\
 	$(UNIT_SRC)/fifo/fifo/gv11b	\
diff --git a/userspace/required_tests.ini b/userspace/required_tests.ini
index d57f945e0..5d008dcad 100644
--- a/userspace/required_tests.ini
+++ b/userspace/required_tests.ini
@@ -963,17 +963,6 @@ test_ispow2.is_powof2=0
 test_rounddown_powoftwo.rounddown_pow2=0
 test_roundup_powoftwo.roundup_pow2=0
 
-[posix_mockio]
-test_readl.bar1_readl=0
-test_readl.readl=0
-test_readl.readl_impl=0
-test_register_io_callbacks.register_io_callbacks=0
-test_register_space.test_register_space=0
-test_writel.bar1_writel=0
-test_writel.usermode_writel=0
-test_writel.writel=0
-test_writel.writel_check=0
-
 [posix_ossched]
 test_current_pid.current_pid=0
 test_current_tid.current_tid=0
@@ -1115,4 +1104,3 @@ test_branches.branches=0
 test_deinit.deinit=0
 test_enqueue.enqueue=0
 test_init.init=0
-
diff --git a/userspace/units/acr/Makefile b/userspace/units/acr/Makefile
index 873a11d07..e67607aa0 100644
--- a/userspace/units/acr/Makefile
+++ b/userspace/units/acr/Makefile
@@ -1,4 +1,4 @@
-# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+# Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
@@ -24,20 +24,15 @@ OBJS   = nvgpu-acr.o
 MODULE = nvgpu-acr
 
 LIB_PATHS += -lfalcon_utf \
-	     -lnvgpu-gr \
-	     -lmock-iospace
+	     -lnvgpu-gr
 
 include ../Makefile.units
 
 lib$(MODULE).so: falcon_utf \
-		 nvgpu-gr \
-		 mock-iospace
+		 nvgpu-gr
 
 falcon_utf:
 	$(MAKE) -C ../falcon
 
 nvgpu-gr:
 	$(MAKE) -C ../gr
-
-mock-iospace:
-	$(MAKE) -C ../mock-iospace
diff --git a/userspace/units/acr/Makefile.tmk b/userspace/units/acr/Makefile.tmk
index 9a445d2de..6742b95db 100644
--- a/userspace/units/acr/Makefile.tmk
+++ b/userspace/units/acr/Makefile.tmk
@@ -29,8 +29,7 @@ NVGPU_UNIT_SRCS=nvgpu-acr.c
 
 NVGPU_UNIT_INTERFACE_DIRS := \
 	$(NV_COMPONENT_DIR)/../falcon \
-	$(NV_COMPONENT_DIR)/../gr \
-	$(NV_COMPONENT_DIR)/../mock-iospace
+	$(NV_COMPONENT_DIR)/../gr
 
 include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
 
@@ -39,4 +38,3 @@ include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
 # tab-width: 8
 # End:
 # vi: set tabstop=8 noexpandtab:
-
diff --git a/userspace/units/acr/nvgpu-acr.c b/userspace/units/acr/nvgpu-acr.c
index f4841960f..5f624a924 100644
--- a/userspace/units/acr/nvgpu-acr.c
+++ b/userspace/units/acr/nvgpu-acr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,20 +20,26 @@
  * DEALINGS IN THE SOFTWARE.
  */
 #include <stdlib.h>
+
 #include <unit/unit.h>
 #include <unit/io.h>
+
 #include <nvgpu/types.h>
 #include <nvgpu/acr.h>
 #include <nvgpu/falcon.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pmu.h>
 #include <nvgpu/hal_init.h>
-#include <nvgpu/posix/io.h>
-#include <nvgpu/posix/posix-fault-injection.h>
 #include <nvgpu/lock.h>
 #include <nvgpu/firmware.h>
+
 #include <nvgpu/gr/gr.h>
 
+#include <nvgpu/posix/probe.h>
+#include <nvgpu/posix/io.h>
+#include <nvgpu/posix/posix-fault-injection.h>
+#include <nvgpu/posix/soc_fuse.h>
+
 #include <os/posix/os_posix.h>
 
 #include <common/acr/acr_wpr.h>
@@ -46,98 +52,18 @@
 #include <nvgpu/hw/gv11b/hw_flush_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_falcon_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
-#include <nvgpu/posix/soc_fuse.h>
 
 #include "hal/fuse/fuse_gm20b.h"
 
 #include "nvgpu-acr.h"
 #include "../falcon/falcon_utf.h"
 #include "../gr/nvgpu-gr-gv11b.h"
-#include "../mock-iospace/include/gv11b_mock_regs.h"
-
-
-#define NV_PMC_BOOT_0_ARCHITECTURE_GV110        (0x00000015 << \
-						NVGPU_GPU_ARCHITECTURE_SHIFT)
-#define NV_PMC_BOOT_0_IMPLEMENTATION_B          0xB
-
-#define NV_PMC_BOOT_0_ARCHITECTURE_INVALID	(0x00000018 << \
-						NVGPU_GPU_ARCHITECTURE_SHIFT)
-#define NV_PMC_BOOT_0_IMPLEMENTATION_INVALID	0xD
-
-#define NV_PBB_FBHUB_REGSPACE 0x100B00
-#define NUM_REG_SPACES 10U
 
 #define BAR0_ERRORS_NUM 11
 
 struct utf_falcon *pmu_flcn, *gpccs_flcn;
 static bool mailbox_error;
 
-struct gr_test_reg_details {
-	int idx;
-	u32 base;
-	u32 size;
-	const u32 *data;
-};
-
-struct gr_test_reg_details gr_gv11b_reg_space[NUM_REG_SPACES] = {
-	[0] = {
-		.idx = gv11b_master_reg_idx,
-		.base = 0x00000000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[1] = {
-		.idx = gv11b_pri_reg_idx,
-		.base = 0x00120000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[2] = {
-		.idx = gv11b_fuse_reg_idx,
-		.base = 0x00021000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[3] = {
-		.idx = gv11b_top_reg_idx,
-		.base = 0x00022400,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[4] = {
-		.idx = gv11b_gr_reg_idx,
-		.base = 0x00400000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[5] = {
-		.idx = gv11b_fifo_reg_idx,
-		.base = 0x2000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[6] = { /* NV_FBIO_REGSPACE */
-		.base = 0x100800,
-		.size = 0x7FF,
-		.data = NULL,
-	},
-	[7] = { /* NV_PLTCG_LTCS_REGSPACE */
-		.base = 0x17E200,
-		.size = 0x100,
-		.data = NULL,
-	},
-	[8] = { /* NV_PFB_HSHUB_ACTIVE_LTCS REGSPACE */
-		.base = 0x1FBC20,
-		.size = 0x4,
-		.data = NULL,
-	},
-	[9] = { /* NV_PCCSR_CHANNEL REGSPACE */
-		.base = 0x800004,
-		.size = 0x1F,
-		.data = NULL,
-	},
-};
-
 static int stub_gv11b_bar0_error_status(struct gk20a *g, u32 *bar0_status,
 	u32 *etype)
 {
@@ -246,86 +172,10 @@ static void utf_falcon_register_io(struct gk20a *g)
 	nvgpu_posix_register_io(g, &utf_falcon_reg_callbacks);
 }
 
-static int gr_io_add_reg_space(struct unit_module *m, struct gk20a *g)
-{
-	int ret = UNIT_SUCCESS;
-	u32 i = 0, j = 0;
-	u32 base, size;
-	struct nvgpu_posix_io_reg_space *gr_io_reg;
-
-	for (i = 0; i < NUM_REG_SPACES; i++) {
-		base = gr_gv11b_reg_space[i].base;
-		size = gr_gv11b_reg_space[i].size;
-		if (size == 0) {
-			struct mock_iospace iospace = {0};
-			ret = gv11b_get_mock_iospace(gr_gv11b_reg_space[i].idx,
-				&iospace);
-			if (ret != 0) {
-				unit_err(m, "failed to get reg space for %08x\n",
-					base);
-				goto clean_init_reg_space;
-			}
-			gr_gv11b_reg_space[i].data = iospace.data;
-			gr_gv11b_reg_space[i].size = size = iospace.size;
-		}
-
-		if (nvgpu_posix_io_add_reg_space(g, base, size) != 0) {
-			unit_err(m, "failed to add reg space for %08x\n", base);
-			ret = UNIT_FAIL;
-			goto clean_init_reg_space;
-		}
-
-		gr_io_reg = nvgpu_posix_io_get_reg_space(g, base);
-		if (gr_io_reg == NULL) {
-			unit_err(m, "failed to get reg space for %08x\n", base);
-			ret = UNIT_FAIL;
-			goto clean_init_reg_space;
-		}
-
-		if (gr_gv11b_reg_space[i].data != NULL) {
-			memcpy(gr_io_reg->data, gr_gv11b_reg_space[i].data, size);
-		} else {
-			memset(gr_io_reg->data, 0, size);
-		}
-	}
-	return ret;
-
-clean_init_reg_space:
-	for (j = 0; j < i; j++) {
-		base = gr_gv11b_reg_space[j].base;
-		nvgpu_posix_io_delete_reg_space(g, base);
-	}
-	return ret;
-}
-
-static void gr_io_delete_reg_space(struct unit_module *m, struct gk20a *g)
-{
-	u32 i = 0;
-
-	for (i = 0; i < NUM_REG_SPACES; i++) {
-		u32 base = gr_gv11b_reg_space[i].base;
-		nvgpu_posix_io_delete_reg_space(g, base);
-	}
-}
-
-static void gr_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
-{
-	gr_io_delete_reg_space(m, g);
-}
-
 static int init_acr_falcon_test_env(struct unit_module *m, struct gk20a *g)
 {
 	int err = 0;
 
-	nvgpu_posix_io_init_reg_space(g);
-	/*
-	 * Initialise GR registers
-	 */
-	if (gr_io_add_reg_space(m, g) == UNIT_FAIL) {
-		unit_err(m, "failed to get initialized GR reg space\n");
-		return UNIT_FAIL;
-	}
-
 	utf_falcon_register_io(g);
 
 	/*
@@ -1120,7 +970,7 @@ static int free_falcon_test_env(struct unit_module *m, struct gk20a *g,
 	 */
 	nvgpu_utf_falcon_free(g, pmu_flcn);
 	nvgpu_utf_falcon_free(g, gpccs_flcn);
-	gr_cleanup_gv11b_reg_space(m, g);
+
 	return UNIT_SUCCESS;
 }
 
diff --git a/userspace/units/bus/nvgpu-bus.c b/userspace/units/bus/nvgpu-bus.c
index d1a335b20..68b776879 100644
--- a/userspace/units/bus/nvgpu-bus.c
+++ b/userspace/units/bus/nvgpu-bus.c
@@ -129,9 +129,6 @@ int test_bus_setup(struct unit_module *m, struct gk20a *g, void *args)
 					mc_gp10b_intr_stall_unit_config;
 	g->ops.ptimer.isr = gk20a_ptimer_isr;
 
-	/* Init register space */
-	nvgpu_posix_io_init_reg_space(g);
-
 	/* Map register space NV_PRIV_MASTER */
 	if (nvgpu_posix_io_add_reg_space(g, NV_PBUS_START, NV_PBUS_SIZE) != 0) {
 		unit_err(m, "%s: failed to register space: NV_PBUS\n",
diff --git a/userspace/units/ce/nvgpu-ce.c b/userspace/units/ce/nvgpu-ce.c
index 52c3dd7fc..422b873a3 100644
--- a/userspace/units/ce/nvgpu-ce.c
+++ b/userspace/units/ce/nvgpu-ce.c
@@ -108,7 +108,6 @@ int test_setup_env(struct unit_module *m,
 			  struct gk20a *g, void *args)
 {
 	/* Create mc register space */
-	nvgpu_posix_io_init_reg_space(g);
 	if (nvgpu_posix_io_add_reg_space(g, CE_ADDR_SPACE_START,
 						CE_ADDR_SPACE_SIZE) != 0) {
 		unit_err(m, "%s: failed to create register space\n",
diff --git a/userspace/units/cg/nvgpu-cg.c b/userspace/units/cg/nvgpu-cg.c
index f3671ccf5..25ee1ce31 100644
--- a/userspace/units/cg/nvgpu-cg.c
+++ b/userspace/units/cg/nvgpu-cg.c
@@ -303,7 +303,6 @@ static struct nvgpu_posix_io_callbacks cg_callbacks = {
 static int init_test_env(struct unit_module *m, struct gk20a *g, void *args)
 {
 	nvgpu_posix_register_io(g, &cg_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/*
 	 * Fuse register fuse_opt_priv_sec_en_r() is read during init_hal hence
diff --git a/userspace/units/falcon/falcon_tests/falcon.c b/userspace/units/falcon/falcon_tests/falcon.c
index 2da42ee3a..e925c9f27 100644
--- a/userspace/units/falcon/falcon_tests/falcon.c
+++ b/userspace/units/falcon/falcon_tests/falcon.c
@@ -137,7 +137,6 @@ static int init_falcon_test_env(struct unit_module *m, struct gk20a *g)
 {
 	int err = 0;
 
-	nvgpu_posix_io_init_reg_space(g);
 	utf_falcon_register_io(g);
 
 	/*
@@ -365,14 +364,6 @@ int test_falcon_sw_init_free(struct unit_module *m, struct gk20a *g,
 {
 	int err;
 
-	/* verify that sw_init fails when g->params.gpu_arch|impl are invalid */
-	err = nvgpu_falcon_sw_init(g, FALCON_ID_FECS);
-	if (err != -EINVAL) {
-		unit_return_fail(m, "falcon initialized for invalid GPU\n");
-	}
-
-	nvgpu_falcon_sw_free(g, FALCON_ID_FECS);
-
 	/* initialize test setup */
 	if (init_falcon_test_env(m, g) != 0) {
 		unit_return_fail(m, "Module init failed\n");
diff --git a/userspace/units/fb/fb_fusa.c b/userspace/units/fb/fb_fusa.c
index a76a31a05..9843cec47 100644
--- a/userspace/units/fb/fb_fusa.c
+++ b/userspace/units/fb/fb_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -86,7 +86,6 @@ static struct nvgpu_posix_io_callbacks fb_callbacks = {
 static int fb_gv11b_init(struct unit_module *m, struct gk20a *g, void *args)
 {
 	nvgpu_posix_register_io(g, &fb_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB */
 	if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), SZ_4K) != 0) {
@@ -146,12 +145,14 @@ struct unit_module_test fb_tests[] = {
 		fb_mmu_fault_gv11b_handle_bar2_fault, NULL, 0),
 	UNIT_TEST(fb_intr_gv11b_init_test, fb_intr_gv11b_init_test, NULL, 0),
 	UNIT_TEST(fb_intr_gv11b_isr_test, fb_intr_gv11b_isr_test, NULL, 0),
+
 	UNIT_TEST(fb_intr_gv11b_ecc_test_L2TLB, fb_intr_gv11b_ecc_test,
 		(void *) TEST_ECC_L2TLB, 0),
 	UNIT_TEST(fb_intr_gv11b_ecc_test_HUBTLB, fb_intr_gv11b_ecc_test,
 		(void *) TEST_ECC_HUBTLB, 0),
 	UNIT_TEST(fb_intr_gv11b_ecc_test_FILLUNIT, fb_intr_gv11b_ecc_test,
 		(void *) TEST_ECC_FILLUNIT, 0),
+
 	UNIT_TEST(fb_gv11b_cleanup, fb_gv11b_cleanup, NULL, 0),
 };
 
diff --git a/userspace/units/fbp/nvgpu-fbp.c b/userspace/units/fbp/nvgpu-fbp.c
index 6866a991b..8530063e0 100644
--- a/userspace/units/fbp/nvgpu-fbp.c
+++ b/userspace/units/fbp/nvgpu-fbp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -72,9 +72,6 @@ int test_fbp_setup(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.top.get_max_fbps_count = gm20b_top_get_max_fbps_count;
 	g->ops.fuse.fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp;
 
-	/* Init register space */
-	nvgpu_posix_io_init_reg_space(g);
-
 	/* Map register space for FUSE_STATUS_OPT_FBP */
 	if (nvgpu_posix_io_add_reg_space(g, fuse_status_opt_fbp_r(), 0x4)
 									!= 0) {
diff --git a/userspace/units/fifo/Makefile b/userspace/units/fifo/Makefile
index 5c3bcb933..e66cb47d3 100644
--- a/userspace/units/fifo/Makefile
+++ b/userspace/units/fifo/Makefile
@@ -1,4 +1,4 @@
-# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+# Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
@@ -23,12 +23,5 @@
 OBJS   = nvgpu-fifo-common.o nvgpu-fifo-gv11b.o
 
 MODULE = nvgpu-fifo-common
-LIB_PATHS += -lmock-iospace
 
 include ../Makefile.units
-
-lib$(MODULE).so: mock-iospace
-
-mock-iospace:
-	$(MAKE) -C ../mock-iospace/
-
diff --git a/userspace/units/fifo/Makefile.tmk b/userspace/units/fifo/Makefile.tmk
index f78dd8883..2f7895019 100644
--- a/userspace/units/fifo/Makefile.tmk
+++ b/userspace/units/fifo/Makefile.tmk
@@ -1,6 +1,6 @@
 ################################### tell Emacs this is a -*- makefile-gmake -*-
 #
-# Copyright (c) 2019 NVIDIA CORPORATION.  All Rights Reserved.
+# Copyright (c) 2019-2020 NVIDIA CORPORATION.  All Rights Reserved.
 #
 # NVIDIA CORPORATION and its licensors retain all intellectual property
 # and proprietary rights in and to this software, related documentation
@@ -17,9 +17,6 @@
 NVGPU_UNIT_NAME = nvgpu-fifo-common
 NVGPU_UNIT_SRCS = nvgpu-fifo-common.c nvgpu-fifo-gv11b.c
 
-NVGPU_UNIT_INTERFACE_DIRS := \
-			$(NV_SOURCE)/kernel/nvgpu/userspace/units/mock-iospace
-
 include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
 
 # Local Variables:
diff --git a/userspace/units/fifo/libnvgpu-fifo-common.export b/userspace/units/fifo/libnvgpu-fifo-common.export
index dc2d3d6a2..479d0b891 100644
--- a/userspace/units/fifo/libnvgpu-fifo-common.export
+++ b/userspace/units/fifo/libnvgpu-fifo-common.export
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+# Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
@@ -26,4 +26,3 @@ test_fifo_remove_support
 test_fifo_subtest_pruned
 test_fifo_flags_str
 test_fifo_setup_gv11b_reg_space
-test_fifo_cleanup_gv11b_reg_space
diff --git a/userspace/units/fifo/nvgpu-fifo-common.c b/userspace/units/fifo/nvgpu-fifo-common.c
index d386cf600..481abb515 100644
--- a/userspace/units/fifo/nvgpu-fifo-common.c
+++ b/userspace/units/fifo/nvgpu-fifo-common.c
@@ -171,10 +171,6 @@ int test_fifo_init_support(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.mm.init_mm_support(g);
 
 	err = nvgpu_fifo_init_support(g);
-	if (err != 0) {
-		test_fifo_cleanup_gv11b_reg_space(m, g);
-		goto fail;
-	}
 
 	/* Do not allocate from vidmem */
 	nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
@@ -192,8 +188,5 @@ int test_fifo_remove_support(struct unit_module *m,
 		g->fifo.remove_support(&g->fifo);
 	}
 
-	test_fifo_cleanup_gv11b_reg_space(m, g);
-
 	return UNIT_SUCCESS;
 }
-
diff --git a/userspace/units/fifo/nvgpu-fifo-gv11b.c b/userspace/units/fifo/nvgpu-fifo-gv11b.c
index aba081d93..c81c16685 100644
--- a/userspace/units/fifo/nvgpu-fifo-gv11b.c
+++ b/userspace/units/fifo/nvgpu-fifo-gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,23 +20,15 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#include <stdlib.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <unit/io.h>
-#include <unit/unit.h>
+#include <unit/module.h>
+
+#include <nvgpu/gk20a.h>
 
 #include <nvgpu/posix/io.h>
 #include <nvgpu/posix/soc_fuse.h>
 
-#include <nvgpu/gk20a.h>
-
 #include "hal/fuse/fuse_gm20b.h"
 
-#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
-
-#include <gv11b_mock_regs.h>
-
 #include "nvgpu-fifo-gv11b.h"
 
 /*
@@ -84,176 +76,10 @@ static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
 	.tegra_fuse_readl = tegra_fuse_readl_access_reg_fn,
 };
 
-struct test_reg_space {
-	int idx;
-	u32 base;
-	u32 size;
-	const u32 *data;
-	void (*init)(u32 *data, u32 size);
-};
-
-static void init_reg_space_usermode(u32 *data, u32 size)
-{
-	u32 i;
-
-	for (i = 0U; i < size/4U; i++) {
-		data[i] = 0xbadf1100;
-	}
-}
-
-#define NUM_REG_SPACES 11U
-struct test_reg_space reg_spaces[NUM_REG_SPACES] = {
-	[0] = {	/* FUSE */
-		.idx = gv11b_fuse_reg_idx,
-		.base = 0x00021000,
-		.size = 0,
-		.data = NULL,
-	},
-	[1] = { /* MASTER */
-		.idx = gv11b_master_reg_idx,
-		.base = 0x00000000,
-		.size = 0,
-		.data = NULL,
-	},
-	[2] = { /* TOP */
-		.idx = gv11b_top_reg_idx,
-		.base = 0x22400,
-		.size = 0,
-		.data = NULL,
-	},
-	[3] = { /* PBDMA */
-		.idx = gv11b_pbdma_reg_idx,
-		.base = 0x00040000,
-		.size = 0,
-		.data = NULL,
-	},
-	[4] = { /* CCSR */
-		.idx = gv11b_ccsr_reg_idx,
-		.base = 0x00800000,
-		.size = 0,
-		.data = NULL,
-	},
-	[5] = { /* FIFO */
-		.idx = gv11b_fifo_reg_idx,
-		.base = 0x2000,
-		.size = 0,
-		.data = NULL,
-	},
-	[6] = { /* USERMODE */
-		.base = usermode_cfg0_r(),
-		.size = 0x10000,
-		.data = NULL,
-		.init = init_reg_space_usermode,
-	},
-	[7] = { /* CE */
-		.base = 0x104000,
-		.size = 0x2000,
-		.data = NULL,
-	},
-	[8] = { /* PBUS */
-		.base = 0x1000,
-		.size = 0x1000,
-		.data = NULL,
-	},
-	[9] = { /* HSUB_COMMON */
-		.base = 0x1fbc00,
-		.size = 0x400,
-		.data = NULL,
-	},
-	[10] = { /* PFB */
-		.base = 0x100000,
-		.size = 0x1000,
-		.data = NULL,
-	},
-};
-
-static void fifo_io_delete_reg_spaces(struct unit_module *m, struct gk20a *g)
-{
-	u32 i = 0;
-
-	for (i = 0; i < NUM_REG_SPACES; i++) {
-		u32 base = reg_spaces[i].base;
-
-		nvgpu_posix_io_delete_reg_space(g, base);
-	}
-}
-
-static int fifo_io_add_reg_spaces(struct unit_module *m, struct gk20a *g)
-{
-	int ret = 0;
-	u32 i = 0, j = 0;
-	u32 base, size;
-	struct nvgpu_posix_io_reg_space *reg_space;
-
-	for (i = 0; i < NUM_REG_SPACES; i++) {
-		base = reg_spaces[i].base;
-		size = reg_spaces[i].size;
-		if (size == 0) {
-			struct mock_iospace iospace = {0};
-
-			ret = gv11b_get_mock_iospace(reg_spaces[i].idx,
-					&iospace);
-			if (ret != 0) {
-				unit_err(m, "failed to get reg space for %08x\n",
-						base);
-				goto clean_init_reg_space;
-			}
-			reg_spaces[i].data = iospace.data;
-			reg_spaces[i].size = size = iospace.size;
-		}
-		if (nvgpu_posix_io_add_reg_space(g, base, size) != 0) {
-			unit_err(m, "failed to add reg space for %08x\n", base);
-			ret = -ENOMEM;
-			goto clean_init_reg_space;
-		}
-
-		reg_space = nvgpu_posix_io_get_reg_space(g, base);
-		if (reg_space == NULL) {
-			unit_err(m, "failed to get reg space for %08x\n", base);
-			ret = -EINVAL;
-			goto clean_init_reg_space;
-		} else {
-			unit_info(m, " IO reg space %08x:%08x\n", base + size -1, base);
-		}
-
-		if (reg_spaces[i].data != NULL) {
-			memcpy(reg_space->data, reg_spaces[i].data, size);
-		} else {
-			if (reg_spaces[i].init != NULL) {
-				reg_spaces[i].init(reg_space->data, size);
-			} else {
-				memset(reg_space->data, 0, size);
-			}
-		}
-	}
-
-	return ret;
-
-clean_init_reg_space:
-	for (j = 0; j < i; j++) {
-		base = reg_spaces[j].base;
-		nvgpu_posix_io_delete_reg_space(g, base);
-	}
-
-	return ret;
-}
 
 int test_fifo_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
 {
-	/* Create register space */
-	nvgpu_posix_io_init_reg_space(g);
-
-	if (fifo_io_add_reg_spaces(m, g) != 0) {
-		unit_err(m, "failed to get initialized reg space\n");
-		return UNIT_FAIL;
-	}
-
 	(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
 
 	return 0;
 }
-
-void test_fifo_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
-{
-	fifo_io_delete_reg_spaces(m, g);
-}
diff --git a/userspace/units/fifo/nvgpu-fifo-gv11b.h b/userspace/units/fifo/nvgpu-fifo-gv11b.h
index 1217b9b34..6fb4302fd 100644
--- a/userspace/units/fifo/nvgpu-fifo-gv11b.h
+++ b/userspace/units/fifo/nvgpu-fifo-gv11b.h
@@ -24,6 +24,5 @@
 #define UNIT_NVGPU_FIFO_GV11B_H
 
 int test_fifo_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g);
-void test_fifo_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g);
 
 #endif /* UNIT_NVGPU_FIFO_GV11B_H */
diff --git a/userspace/units/fuse/nvgpu-fuse.c b/userspace/units/fuse/nvgpu-fuse.c
index 2f5f9daad..ba8d6ef93 100644
--- a/userspace/units/fuse/nvgpu-fuse.c
+++ b/userspace/units/fuse/nvgpu-fuse.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -103,7 +103,6 @@ int test_fuse_device_common_init(struct unit_module *m,
 	struct fuse_test_args *args = (struct fuse_test_args *)__args;
 
 	/* Create fuse register space */
-	nvgpu_posix_io_init_reg_space(g);
 	if (nvgpu_posix_io_add_reg_space(g, args->fuse_base_addr, 0xfff) != 0) {
 		unit_err(m, "%s: failed to create register space\n",
 			 __func__);
diff --git a/userspace/units/gr/Makefile b/userspace/units/gr/Makefile
index 9935f5298..8e5cc82c5 100644
--- a/userspace/units/gr/Makefile
+++ b/userspace/units/gr/Makefile
@@ -1,4 +1,4 @@
-# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+# Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
@@ -23,11 +23,5 @@
 OBJS   = nvgpu-gr.o nvgpu-gr-gv11b.o
 
 MODULE = nvgpu-gr
-LIB_PATHS += -lmock-iospace
 
 include ../Makefile.units
-
-lib$(MODULE).so: mock-iospace
-
-mock-iospace:
-	$(MAKE) -C ../mock-iospace/
diff --git a/userspace/units/gr/Makefile.tmk b/userspace/units/gr/Makefile.tmk
index a98502069..aa43cf501 100644
--- a/userspace/units/gr/Makefile.tmk
+++ b/userspace/units/gr/Makefile.tmk
@@ -1,6 +1,6 @@
 ################################### tell Emacs this is a -*- makefile-gmake -*-
 #
-# Copyright (c) 2019 NVIDIA CORPORATION.  All Rights Reserved.
+# Copyright (c) 2019-2020 NVIDIA CORPORATION.  All Rights Reserved.
 #
 # NVIDIA CORPORATION and its licensors retain all intellectual property
 # and proprietary rights in and to this software, related documentation
@@ -17,9 +17,6 @@
 NVGPU_UNIT_NAME = nvgpu-gr
 NVGPU_UNIT_SRCS = nvgpu-gr.c nvgpu-gr-gv11b.c
 
-NVGPU_UNIT_INTERFACE_DIRS := \
-			$(NV_SOURCE)/kernel/nvgpu/userspace/units/mock-iospace
-
 include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
 
 # Local Variables:
diff --git a/userspace/units/gr/nvgpu-gr-gv11b.c b/userspace/units/gr/nvgpu-gr-gv11b.c
index d97dab115..45e0fb3e2 100644
--- a/userspace/units/gr/nvgpu-gr-gv11b.c
+++ b/userspace/units/gr/nvgpu-gr-gv11b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,13 +21,13 @@
  */
 
 #include <stdlib.h>
-#include <nvgpu/types.h>
 #include <unistd.h>
+
 #include <unit/io.h>
-#include <unit/unit.h>
 
 #include <nvgpu/posix/io.h>
 #include <nvgpu/posix/soc_fuse.h>
+#include <nvgpu/posix/mock-regs.h>
 
 #include <nvgpu/gk20a.h>
 
@@ -36,202 +36,50 @@
 #include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 
-#include <gv11b_mock_regs.h>
-
 #include "nvgpu-gr-gv11b.h"
 
-struct gr_test_reg_info {
-	int idx;
-	u32 base;
-	u32 size;
-	const u32 *data;
-};
-
-#define NUM_REG_SPACES 10U
-struct gr_test_reg_info  gr_gv11b_reg_space[NUM_REG_SPACES] = {
-	[0] = {
-		.idx = gv11b_master_reg_idx,
-		.base = 0x00000000,
-		.size = 0x0,
-		.data = NULL,
-	      },
-	[1] = {
-		.idx = gv11b_pri_reg_idx,
-		.base = 0x00120000,
-		.size = 0x0,
-		.data = NULL,
-	      },
-	[2] = {
-		.idx = gv11b_fuse_reg_idx,
-		.base = 0x00021000,
-		.size = 0x0,
-		.data = NULL,
-	      },
-	[3] = {
-		.idx = gv11b_top_reg_idx,
-		.base = 0x00022400,
-		.size = 0x0,
-		.data = NULL,
-	      },
-	[4] = {
-		.idx = gv11b_gr_reg_idx,
-		.base = 0x00400000,
-		.size = 0x0,
-		.data = NULL,
-	      },
-	[5] = {
-		.idx = gv11b_fifo_reg_idx,
-		.base = 0x2000,
-		.size = 0x0,
-		.data = NULL,
-	      },
-	[6] = { /* NV_FBIO_REGSPACE */
-		.base = 0x100800,
-		.size = 0x7FF,
-		.data = NULL,
-	      },
-	[7] = { /* NV_PLTCG_LTCS_REGSPACE */
+#define NUM_REG_SPACES 1U
+static struct nvgpu_mock_iospace reg_spaces[NUM_REG_SPACES] = {
+	[0] = { /* NV_PLTCG_LTCS_REGSPACE */
 		.base = 0x17E200,
 		.size = 0x100,
 		.data = NULL,
-	      },
-	[8] = { /* NV_PFB_HSHUB_ACTIVE_LTCS REGSPACE */
-		.base = 0x1FBC20,
-		.size = 0x4,
-		.data = NULL,
-	      },
-	[9] = { /* NV_PCCSR_CHANNEL REGSPACE */
-		.base = 0x800004,
-		.size = 0x1F,
-		.data = NULL,
-	      },
+	},
 };
 
-/*
- * Mock I/O
- */
-
-/*
- * Write callback. Forward the write access to the mock IO framework.
- */
-static void writel_access_reg_fn(struct gk20a *g,
-		struct nvgpu_reg_access *access)
-{
-	nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
-}
-
-/*
- * Read callback. Get the register value from the mock IO framework.
- */
-static void readl_access_reg_fn(struct gk20a *g,
-		struct nvgpu_reg_access *access)
-{
-	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
-}
-
-static int tegra_fuse_readl_access_reg_fn(unsigned long offset, u32 *value)
-{
-	if (offset == FUSE_GCPLEX_CONFIG_FUSE_0) {
-		*value = GCPLEX_CONFIG_WPR_ENABLED_MASK;
-	}
-	return 0;
-}
-
-static struct nvgpu_posix_io_callbacks gr_test_reg_callbacks = {
-	/* Write APIs all can use the same accessor. */
-	.writel          = writel_access_reg_fn,
-	.writel_check    = writel_access_reg_fn,
-	.bar1_writel     = writel_access_reg_fn,
-	.usermode_writel = writel_access_reg_fn,
-
-	/* Likewise for the read APIs. */
-	.__readl         = readl_access_reg_fn,
-	.readl           = readl_access_reg_fn,
-	.bar1_readl      = readl_access_reg_fn,
-
-	.tegra_fuse_readl = tegra_fuse_readl_access_reg_fn,
-};
-
-static void gr_io_delete_reg_space(struct unit_module *m, struct gk20a *g)
+static void delete_reg_space(struct unit_module *m, struct gk20a *g)
 {
 	u32 i = 0;
 
 	for (i = 0; i < NUM_REG_SPACES; i++) {
-		u32 base = gr_gv11b_reg_space[i].base;
-		nvgpu_posix_io_delete_reg_space(g, base);
+		nvgpu_posix_io_delete_reg_space(g, reg_spaces[i].base);
 	}
 }
 
-static int gr_io_add_reg_space(struct unit_module *m, struct gk20a *g)
+static int add_reg_space(struct unit_module *m, struct gk20a *g)
 {
-	int ret = UNIT_SUCCESS;
-	u32 i = 0, j = 0;
-	u32 base, size;
-	struct nvgpu_posix_io_reg_space *gr_io_reg;
+	u32 i;
+	int err;
 
 	for (i = 0; i < NUM_REG_SPACES; i++) {
-		base = gr_gv11b_reg_space[i].base;
-		size = gr_gv11b_reg_space[i].size;
-		if (size == 0) {
-			struct mock_iospace iospace = {0};
+		struct nvgpu_mock_iospace *iospace = &reg_spaces[i];
 
-			ret = gv11b_get_mock_iospace(gr_gv11b_reg_space[i].idx,
-					&iospace);
-			if (ret != 0) {
-				unit_err(m, "failed to get reg space for %08x\n",
-						base);
-				goto clean_init_reg_space;
-			}
-			gr_gv11b_reg_space[i].data = iospace.data;
-			gr_gv11b_reg_space[i].size = size = iospace.size;
-		}
-		if (nvgpu_posix_io_add_reg_space(g, base, size) != 0) {
-			unit_err(m, "failed to add reg space for %08x\n", base);
-			ret = UNIT_FAIL;
-			goto clean_init_reg_space;
-		}
-
-		gr_io_reg = nvgpu_posix_io_get_reg_space(g, base);
-		if (gr_io_reg == NULL) {
-			unit_err(m, "failed to get reg space for %08x\n", base);
-			ret = UNIT_FAIL;
-			goto clean_init_reg_space;
-		}
-
-		if (gr_gv11b_reg_space[i].data != NULL) {
-			memcpy(gr_io_reg->data, gr_gv11b_reg_space[i].data, size);
-		} else {
-			memset(gr_io_reg->data, 0, size);
-		}
+		err = nvgpu_posix_io_add_reg_space(g, iospace->base,
+						   iospace->size);
+		nvgpu_assert(err == 0);
 	}
 
-	return ret;
-
-clean_init_reg_space:
-	for (j = 0; j < i; j++) {
-		base = gr_gv11b_reg_space[j].base;
-		nvgpu_posix_io_delete_reg_space(g, base);
-	}
-
-	return ret;
+	return 0;
 }
 
 int test_gr_setup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
 {
-	/* Create register space */
-	nvgpu_posix_io_init_reg_space(g);
-
-	if (gr_io_add_reg_space(m, g) == UNIT_FAIL) {
-		unit_err(m, "failed to get initialized reg space\n");
-		return UNIT_FAIL;
-	}
-
-	(void)nvgpu_posix_register_io(g, &gr_test_reg_callbacks);
+	nvgpu_assert(add_reg_space(m, g) == 0);
 
 	return 0;
 }
 
 void test_gr_cleanup_gv11b_reg_space(struct unit_module *m, struct gk20a *g)
 {
-	gr_io_delete_reg_space(m, g);
+	delete_reg_space(m, g);
 }
diff --git a/userspace/units/gr/nvgpu-gr.c b/userspace/units/gr/nvgpu-gr.c
index 8fedd8278..1ec8469a5 100644
--- a/userspace/units/gr/nvgpu-gr.c
+++ b/userspace/units/gr/nvgpu-gr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,10 +39,6 @@
 #include "nvgpu-gr.h"
 #include "nvgpu-gr-gv11b.h"
 
-#define NV_PMC_BOOT_0_ARCHITECTURE_GV110	(0x00000015 << \
-					NVGPU_GPU_ARCHITECTURE_SHIFT)
-#define NV_PMC_BOOT_0_IMPLEMENTATION_B		0xB
-
 int test_gr_init_setup(struct unit_module *m, struct gk20a *g, void *args)
 {
 	int err;
@@ -52,21 +48,6 @@ int test_gr_init_setup(struct unit_module *m, struct gk20a *g, void *args)
 		goto fail;
 	}
 
-	/*
-	 * HAL init parameters for gv11b
-	 */
-	g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
-	g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
-
-	/*
-	 * HAL init required for getting
-	 * the falcon ops initialized.
-	 */
-	err = nvgpu_init_hal(g);
-	if (err != 0) {
-		unit_return_fail(m, "nvgpu_init_hal failed\n");
-	}
-
 	/*
 	 * Allocate gr unit
 	 */
diff --git a/userspace/units/init/nvgpu-init.c b/userspace/units/init/nvgpu-init.c
index 2e8afc1d2..baba2d2a7 100644
--- a/userspace/units/init/nvgpu-init.c
+++ b/userspace/units/init/nvgpu-init.c
@@ -44,7 +44,7 @@
 /* value for GV11B */
 #define MC_BOOT_0_GV11B (NVGPU_GPUID_GV11B << 20)
 /* to set the security fuses */
-#define GP10B_FUSE_REG_BASE		0x00021000U
+#define GP10B_FUSE_REG_BASE		0x21000
 #define GP10B_FUSE_OPT_PRIV_SEC_EN	(GP10B_FUSE_REG_BASE+0x434U)
 
 #define assert(cond) unit_assert(cond, goto fail)
@@ -52,37 +52,6 @@
  * Mock I/O
  */
 
-/*
- * Write callback. Forward the write access to the mock IO framework.
- */
-static void writel_access_reg_fn(struct gk20a *g,
-				 struct nvgpu_reg_access *access)
-{
-	nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
-}
-
-/*
- * Read callback. Get the register value from the mock IO framework.
- */
-static void readl_access_reg_fn(struct gk20a *g,
-				struct nvgpu_reg_access *access)
-{
-	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
-}
-
-static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
-	/* Write APIs all can use the same accessor. */
-	.writel          = writel_access_reg_fn,
-	.writel_check    = writel_access_reg_fn,
-	.bar1_writel     = writel_access_reg_fn,
-	.usermode_writel = writel_access_reg_fn,
-
-	/* Likewise for the read APIs. */
-	.__readl         = readl_access_reg_fn,
-	.readl           = readl_access_reg_fn,
-	.bar1_readl      = readl_access_reg_fn,
-};
-
 /*
  * Replacement functions that can be assigned to function pointers
  */
@@ -130,31 +99,12 @@ static void no_return_u32_param(struct gk20a *g, u32 dummy)
 int test_setup_env(struct unit_module *m,
 			  struct gk20a *g, void *args)
 {
-	/* Create mc register space */
-	nvgpu_posix_io_init_reg_space(g);
-	if (nvgpu_posix_io_add_reg_space(g, mc_boot_0_r(), 0xfff) != 0) {
-		unit_err(m, "%s: failed to create register space\n",
-			 __func__);
-		return UNIT_FAIL;
-	}
-	/* Create fuse register space */
-	if (nvgpu_posix_io_add_reg_space(g, GP10B_FUSE_REG_BASE, 0xfff) != 0) {
-		unit_err(m, "%s: failed to create register space\n",
-			 __func__);
-		return UNIT_FAIL;
-	}
-	(void)nvgpu_posix_register_io(g, &test_reg_callbacks);
-
 	return UNIT_SUCCESS;
 }
 
 int test_free_env(struct unit_module *m,
 			 struct gk20a *g, void *args)
 {
-	/* Free mc register space */
-	nvgpu_posix_io_delete_reg_space(g, mc_boot_0_r());
-	nvgpu_posix_io_delete_reg_space(g, GP10B_FUSE_REG_BASE);
-
 	/* Clean up quiesce thread */
 	nvgpu_sw_quiesce_remove_support(g);
 
@@ -408,18 +358,6 @@ int test_hal_init(struct unit_module *m,
 	u32 i;
 	struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
 
-	nvgpu_posix_io_writel_reg_space(g, mc_boot_0_r(), MC_BOOT_0_GV11B);
-	nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x0);
-	if (nvgpu_detect_chip(g) != 0) {
-		unit_err(m, "%s: failed to init HAL\n", __func__);
-		return UNIT_FAIL;
-	}
-
-	if (strcmp(g->name, "gv11b") != 0) {
-		unit_err(m, "%s: initialized wrong HAL!\n", __func__);
-		return UNIT_FAIL;
-	}
-
 	/* Branch test for check if already inited the hal */
 	if (nvgpu_detect_chip(g) != 0) {
 		unit_err(m, "%s: failed to init HAL\n", __func__);
@@ -435,15 +373,6 @@ int test_hal_init(struct unit_module *m,
 	}
 	p->is_soc_t194_a01 = false;
 
-	/* Negative testing for secure fuse */
-	g->params.gpu_arch = 0;
-	nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x1);
-	if (nvgpu_detect_chip(g) == 0) {
-		unit_err(m, "%s: HAL init failed to detect incorrect security\n",
-			 __func__);
-		return UNIT_FAIL;
-	}
-
 	/* Negative testing for invalid GPU version */
 	nvgpu_posix_io_writel_reg_space(g, GP10B_FUSE_OPT_PRIV_SEC_EN, 0x0);
 	for (i = 0; i < ARRAY_SIZE(invalid_mc_boot_0); i++) {
diff --git a/userspace/units/io/common_io.c b/userspace/units/io/common_io.c
index 039d0e522..78ef2ac93 100644
--- a/userspace/units/io/common_io.c
+++ b/userspace/units/io/common_io.c
@@ -52,7 +52,6 @@ static struct nvgpu_posix_io_callbacks ut_common_io_reg_callbacks = {
 
 int test_writel_check(struct unit_module *m, struct gk20a *g, void *args)
 {
-	nvgpu_posix_io_init_reg_space(g);
 	nvgpu_posix_register_io(g, &ut_common_io_reg_callbacks);
 
 	/* Value 0 will force to fail readback call as read API returns
diff --git a/userspace/units/ltc/nvgpu-ltc.c b/userspace/units/ltc/nvgpu-ltc.c
index 4ea9c9d1e..7330d1003 100644
--- a/userspace/units/ltc/nvgpu-ltc.c
+++ b/userspace/units/ltc/nvgpu-ltc.c
@@ -100,7 +100,6 @@ int test_ltc_init_support(struct unit_module *m,
 	struct nvgpu_posix_fault_inj *kmem_fi =
 			nvgpu_kmem_get_fault_injection();
 
-	nvgpu_posix_io_init_reg_space(g);
 	if (nvgpu_posix_io_add_reg_space(g, mc_boot_0_r(), 0xfff) != 0) {
 		unit_err(m, "%s: failed to create register space\n", __func__);
 		return UNIT_FAIL;
@@ -683,5 +682,3 @@ struct unit_module_test nvgpu_ltc_tests[] = {
 };
 
 UNIT_MODULE(nvgpu-ltc, nvgpu_ltc_tests, UNIT_PRIO_NVGPU_TEST);
-
-
diff --git a/userspace/units/mc/nvgpu-mc.c b/userspace/units/mc/nvgpu-mc.c
index c6eb5afd6..4f294f788 100644
--- a/userspace/units/mc/nvgpu-mc.c
+++ b/userspace/units/mc/nvgpu-mc.c
@@ -236,7 +236,6 @@ int test_setup_env(struct unit_module *m,
 			  struct gk20a *g, void *args)
 {
 	/* Create mc register space */
-	nvgpu_posix_io_init_reg_space(g);
 	if (nvgpu_posix_io_add_reg_space(g, MC_ADDR_SPACE_START,
 						MC_ADDR_SPACE_SIZE) != 0) {
 		unit_err(m, "%s: failed to create register space\n",
diff --git a/userspace/units/mm/as/as.c b/userspace/units/mm/as/as.c
index 48bec4940..c8a8830dd 100644
--- a/userspace/units/mm/as/as.c
+++ b/userspace/units/mm/as/as.c
@@ -155,6 +155,7 @@ int test_init_mm(struct unit_module *m, struct gk20a *g, void *args)
 		gv11b_fb_read_mmu_fault_buffer_size;
 	g->ops.fb.init_hw = gv11b_fb_init_hw;
 	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.fb.fb_ecc_init = NULL;
 
 	err = nvgpu_init_mm_support(g);
 	if (err != 0) {
diff --git a/userspace/units/mm/dma/dma.c b/userspace/units/mm/dma/dma.c
index 6ebb1b02e..4ccdc17bd 100644
--- a/userspace/units/mm/dma/dma.c
+++ b/userspace/units/mm/dma/dma.c
@@ -237,7 +237,6 @@ int test_mm_dma_init(struct unit_module *m, struct gk20a *g, void *args)
 	}
 
 	nvgpu_posix_register_io(g, &pramin_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 #ifdef CONFIG_NVGPU_DGPU
 	/* Minimum HAL init for PRAMIN */
diff --git a/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c b/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c
index ce4c196ab..f64f62a61 100644
--- a/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c
+++ b/userspace/units/mm/hal/cache/flush_gk20a_fusa/flush-gk20a-fusa.c
@@ -141,7 +141,6 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 					gv11b_mm_mmu_fault_info_mem_destroy;
 
 	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB_MMU */
 	if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x800) != 0) {
diff --git a/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c b/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c
index 677592ccc..ea98d2487 100644
--- a/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c
+++ b/userspace/units/mm/hal/cache/flush_gv11b_fusa/flush-gv11b-fusa.c
@@ -130,7 +130,6 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 					gv11b_mm_mmu_fault_info_mem_destroy;
 
 	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB_MMU */
 	if (nvgpu_posix_io_add_reg_space(g, flush_fb_flush_r(), 0x800) != 0) {
diff --git a/userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.c b/userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.c
index 9c0406e7f..867a6d54c 100644
--- a/userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.c
+++ b/userspace/units/mm/hal/gp10b_fusa/mm-gp10b-fusa.c
@@ -104,22 +104,23 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	p->mm_is_iommuable = true;
 
 	/* Minimum HALs for page_table */
+	memset(&g->ops.bus, 0, sizeof(g->ops.bus));
+	memset(&g->ops.fb, 0, sizeof(g->ops.fb));
+	g->ops.fb.init_hw = gv11b_fb_init_hw;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
 	g->ops.mm.gmmu.get_default_big_page_size =
 					nvgpu_gmmu_default_big_page_size;
 	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
 	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
-	g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
-	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
 	g->ops.mm.setup_hw = nvgpu_mm_setup_hw;
-	g->ops.fb.init_hw = gv11b_fb_init_hw;
-	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
 	g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
 	g->ops.mm.mmu_fault.info_mem_destroy =
 					gv11b_mm_mmu_fault_info_mem_destroy;
 	g->ops.mc.intr_stall_unit_config = mc_gp10b_intr_stall_unit_config;
 
 	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB_MMU */
 	if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) {
diff --git a/userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.c b/userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.c
index aea3081ae..24cfff08c 100644
--- a/userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.c
+++ b/userspace/units/mm/hal/gv11b_fusa/mm-gv11b-fusa.c
@@ -100,21 +100,22 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	p->mm_is_iommuable = true;
 
 	/* Minimum HALs for page_table */
+	memset(&g->ops.bus, 0, sizeof(g->ops.bus));
+	memset(&g->ops.fb, 0, sizeof(g->ops.fb));
+	g->ops.fb.init_hw = gv11b_fb_init_hw;
+	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
+	g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
+	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
+	g->ops.mc.intr_stall_unit_config = mc_gp10b_intr_stall_unit_config;
 	g->ops.mm.gmmu.get_default_big_page_size =
 					nvgpu_gmmu_default_big_page_size;
 	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
-	g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
-	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
 	g->ops.mm.setup_hw = nvgpu_mm_setup_hw;
-	g->ops.fb.init_hw = gv11b_fb_init_hw;
-	g->ops.fb.intr.enable = gv11b_fb_intr_enable;
 	g->ops.mm.cache.fb_flush = gk20a_mm_fb_flush;
-	g->ops.mc.intr_stall_unit_config = mc_gp10b_intr_stall_unit_config;
 	g->ops.mm.mmu_fault.info_mem_destroy =
 					gv11b_mm_mmu_fault_info_mem_destroy;
 
 	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB_MMU */
 	if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) {
diff --git a/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c b/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
index 6a7d74eba..40be2f1f8 100644
--- a/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
+++ b/userspace/units/mm/hal/mmu_fault/gv11b_fusa/mmu-fault-gv11b-fusa.c
@@ -155,7 +155,6 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 					gv11b_mm_mmu_fault_parse_mmu_fault_info;
 
 	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB_MMU */
 	if (nvgpu_posix_io_add_reg_space(g, fb_mmu_ctrl_r(), 0x800) != 0) {
diff --git a/userspace/units/mm/mm/mm.c b/userspace/units/mm/mm/mm.c
index e8c6e7cc8..661ddf193 100644
--- a/userspace/units/mm/mm/mm.c
+++ b/userspace/units/mm/mm/mm.c
@@ -497,7 +497,6 @@ int test_mm_init_hal(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.mm.setup_hw = int_empty_hal;
 
 	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB_MMU */
 	if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) {
@@ -565,6 +564,7 @@ int test_mm_remove_mm_support(struct unit_module *m, struct gk20a *g,
 		unit_return_fail(m, "nvgpu_pd_cache_init failed ??\n");
 	}
 
+	g->ops.mm.mmu_fault.info_mem_destroy = NULL;
 	g->mm.remove_support(&g->mm);
 
 	if (g->mm.pd_cache != NULL) {
@@ -601,6 +601,8 @@ int test_mm_remove_mm_support(struct unit_module *m, struct gk20a *g,
 int test_mm_page_sizes(struct unit_module *m, struct gk20a *g,
 				void *args)
 {
+	g->ops.mm.gmmu.get_big_page_sizes = NULL;
+
 	if (nvgpu_mm_get_default_big_page_size(g) != SZ_64K) {
 		unit_return_fail(m, "unexpected big page size (1)\n");
 	}
diff --git a/userspace/units/mm/nvgpu_mem/nvgpu_mem.c b/userspace/units/mm/nvgpu_mem/nvgpu_mem.c
index 880569f53..dd24c828a 100644
--- a/userspace/units/mm/nvgpu_mem/nvgpu_mem.c
+++ b/userspace/units/mm/nvgpu_mem/nvgpu_mem.c
@@ -109,7 +109,6 @@ static int init_vidmem_env(struct unit_module *m, struct gk20a *g)
 
 	nvgpu_init_pramin(&g->mm);
 	nvgpu_posix_register_io(g, &pramin_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Minimum HAL init for PRAMIN */
 	g->ops.bus.set_bar0_window = gk20a_bus_set_bar0_window;
@@ -328,6 +327,7 @@ int test_nvgpu_mem_iommu_translate(struct unit_module *m,
 	 * But, mm_is_iommuable = true.
 	 */
 	p->mm_is_iommuable = true;
+	g->ops.mm.gmmu.get_iommu_bit = NULL;
 
 	temp_phys = nvgpu_mem_iommu_translate(g, test_sgl->phys);
 	if (temp_phys != test_sgl->phys) {
diff --git a/userspace/units/mm/page_table_faults/page_table_faults.c b/userspace/units/mm/page_table_faults/page_table_faults.c
index 2e5e0d223..5097baec1 100644
--- a/userspace/units/mm/page_table_faults/page_table_faults.c
+++ b/userspace/units/mm/page_table_faults/page_table_faults.c
@@ -127,22 +127,26 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 					mc_gp10b_intr_nonstall_unit_config;
 
 	/* Minimum HALs for page_table */
-	g->ops.mm.gmmu.get_default_big_page_size =
-		nvgpu_gmmu_default_big_page_size;
-	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
-	g->ops.mm.gmmu.get_max_page_table_levels = gp10b_get_max_page_table_levels;
-	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
-	g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked;
-	g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked;
-	g->ops.mm.gmmu.get_iommu_bit = gp10b_mm_get_iommu_bit;
-	g->ops.mm.gmmu.gpu_phys_addr = gv11b_gpu_phys_addr;
+	memset(&g->ops.bus, 0, sizeof(g->ops.bus));
+	memset(&g->ops.fb, 0, sizeof(g->ops.fb));
 #ifdef CONFIG_NVGPU_COMPRESSION
 	g->ops.fb.compression_page_size = gp10b_fb_compression_page_size;
 #endif
 	g->ops.fb.tlb_invalidate = gm20b_fb_tlb_invalidate;
+
 	g->ops.ramin.init_pdb = gp10b_ramin_init_pdb;
 	g->ops.ramin.alloc_size = gk20a_ramin_alloc_size;
 
+	g->ops.mm.init_inst_block = gv11b_mm_init_inst_block;
+	g->ops.mm.gmmu.get_default_big_page_size =
+		nvgpu_gmmu_default_big_page_size;
+	g->ops.mm.gmmu.get_mmu_levels = gp10b_mm_get_mmu_levels;
+	g->ops.mm.gmmu.get_max_page_table_levels = gp10b_get_max_page_table_levels;
+	g->ops.mm.gmmu.map = nvgpu_gmmu_map_locked;
+	g->ops.mm.gmmu.unmap = nvgpu_gmmu_unmap_locked;
+	g->ops.mm.gmmu.get_iommu_bit = gp10b_mm_get_iommu_bit;
+	g->ops.mm.gmmu.gpu_phys_addr = gv11b_gpu_phys_addr;
+
 	/* New HALs for fault testing */
 	g->ops.mc.is_mmu_fault_pending = gv11b_mc_is_mmu_fault_pending;
 	g->ops.mm.mmu_fault.info_mem_destroy =
@@ -178,7 +182,6 @@ static int init_mm(struct unit_module *m, struct gk20a *g)
 	g->mm.mmu_rd_mem.cpu_va = (void *) 0x30000000;
 
 	nvgpu_posix_register_io(g, &mmu_faults_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Register space: FB_MMU */
 	if (nvgpu_posix_io_add_reg_space(g, fb_niso_intr_r(), 0x800) != 0) {
diff --git a/userspace/units/mock-iospace/Makefile b/userspace/units/mock-iospace/Makefile
deleted file mode 100644
index 8ec2b2c79..000000000
--- a/userspace/units/mock-iospace/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-.SUFFIXES:
-
-OBJS   = gv11b_mock_regs.o
-
-MODULE = mock-iospace
-
-include ../Makefile.units
diff --git a/userspace/units/mock-iospace/Makefile.interface.tmk b/userspace/units/mock-iospace/Makefile.interface.tmk
deleted file mode 100644
index 6ac330108..000000000
--- a/userspace/units/mock-iospace/Makefile.interface.tmk
+++ /dev/null
@@ -1,25 +0,0 @@
-################################### tell Emacs this is a -*- makefile-gmake -*-
-#
-# Copyright (c) 2019, NVIDIA CORPORATION.  All Rights Reserved.
-#
-# NVIDIA CORPORATION and its licensors retain all intellectual property
-# and proprietary rights in and to this software, related documentation
-# and any modifications thereto.  Any use, reproduction, disclosure or
-# distribution of this software and related documentation without an express
-# license agreement from NVIDIA CORPORATION is strictly prohibited.
-#
-# tmake for SW Mobile component makefile
-#
-###############################################################################
-
-ifdef NV_INTERFACE_FLAG_SHARED_LIBRARY_SECTION
-NV_INTERFACE_NAME            := mock-iospace
-NV_INTERFACE_EXPORTS         := lib$(NV_INTERFACE_NAME)
-NV_INTERFACE_PUBLIC_INCLUDES := include
-endif
-
-# Local Variables:
-# indent-tabs-mode: t
-# tab-width: 8
-# End:
-# vi: set tabstop=8 noexpandtab:
diff --git a/userspace/units/mock-iospace/Makefile.tmk b/userspace/units/mock-iospace/Makefile.tmk
deleted file mode 100644
index 5b0fe0050..000000000
--- a/userspace/units/mock-iospace/Makefile.tmk
+++ /dev/null
@@ -1,36 +0,0 @@
-################################### tell Emacs this is a -*- makefile-gmake -*-
-#
-# Copyright (c) 2019, NVIDIA CORPORATION.  All Rights Reserved.
-#
-# NVIDIA CORPORATION and its licensors retain all intellectual property
-# and proprietary rights in and to this software, related documentation
-# and any modifications thereto.  Any use, reproduction, disclosure or
-# distribution of this software and related documentation without an express
-# license agreement from NVIDIA CORPORATION is strictly prohibited.
-#
-# tmake for SW Mobile
-#
-###############################################################################
-ifdef NV_COMPONENT_FLAG_SHARED_LIBRARY_SECTION
-include $(NV_BUILD_START_COMPONENT)
-
-NV_COMPONENT_NAME		:= mock-iospace
-NV_COMPONENT_OWN_INTERFACE_DIR	:= .
-
-NV_COMPONENT_SOURCES		:= gv11b_mock_regs.c
-
-NV_COMPONENT_SYSTEMIMAGE_DIR    := $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)/nvgpu_unit/
-systemimage:: $(NV_COMPONENT_SYSTEMIMAGE_DIR)
-$(NV_COMPONENT_SYSTEMIMAGE_DIR) : $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)
-	 $(MKDIR_P) $@
-NV_COMPONENT_SYSTEMIMAGE_NAME   := libmock-iospace.so
-
-include $(NV_BUILD_SHARED_LIBRARY)
-
-endif
-
-# Local Variables:
-# indent-tabs-mode: t
-# tab-width: 8
-# End:
-# vi: set tabstop=8 noexpandtab:
diff --git a/userspace/units/mock-iospace/include/gv11b_mock_regs.h b/userspace/units/mock-iospace/include/gv11b_mock_regs.h
deleted file mode 100644
index a2ed5cbcf..000000000
--- a/userspace/units/mock-iospace/include/gv11b_mock_regs.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
- *
- * NVIDIA Corporation and its licensors retain all intellectual property and
- * proprietary rights in and to this software and related documentation.  Any
- * use, reproduction, disclosure or distribution of this software and related
- * documentation without an express license agreement from NVIDIA Corporation
- * is strictly prohibited.
- */
-#ifndef NVGPU_GV11B_IOSPACE_H
-#define NVGPU_GV11B_IOSPACE_H
-
-struct mock_iospace {
-	const uint32_t *data;
-	size_t size;
-};
-
-enum gv11b_reg_idx {
-	gv11b_gr_reg_idx = 0,
-	gv11b_fuse_reg_idx,
-	gv11b_master_reg_idx,
-	gv11b_top_reg_idx,
-	gv11b_fifo_reg_idx,
-	gv11b_pri_reg_idx,
-	gv11b_pbdma_reg_idx,
-	gv11b_ccsr_reg_idx,
-	gv11b_last_reg_idx,
-};
-
-int gv11b_get_mock_iospace(int reg_idx, struct mock_iospace *iospace);
-
-#endif
diff --git a/userspace/units/mock-iospace/libmock-iospace.export b/userspace/units/mock-iospace/libmock-iospace.export
deleted file mode 100644
index d547b6e1b..000000000
--- a/userspace/units/mock-iospace/libmock-iospace.export
+++ /dev/null
@@ -1,2 +0,0 @@
-# Copyright (c) 2019, NVIDIA CORPORATION.  All Rights Reserved.
-gv11b_get_mock_iospace
diff --git a/userspace/units/netlist/nvgpu-netlist.c b/userspace/units/netlist/nvgpu-netlist.c
index f3eec1020..24d200d53 100644
--- a/userspace/units/netlist/nvgpu-netlist.c
+++ b/userspace/units/netlist/nvgpu-netlist.c
@@ -92,7 +92,6 @@ int test_netlist_init_support(struct unit_module *m,
 
 	int err = 0;
 
-	nvgpu_posix_io_init_reg_space(g);
 	if (nvgpu_posix_io_add_reg_space(g, mc_boot_0_r(), 0xfff) != 0) {
 		unit_err(m, "%s: failed to create register space\n", __func__);
 		return UNIT_FAIL;
@@ -288,5 +287,3 @@ struct unit_module_test nvgpu_netlist_tests[] = {
 };
 
 UNIT_MODULE(nvgpu-netlist, nvgpu_netlist_tests, UNIT_PRIO_NVGPU_TEST);
-
-
diff --git a/userspace/units/pmu/Makefile b/userspace/units/pmu/Makefile
index 916cd8347..17ee1d1d1 100644
--- a/userspace/units/pmu/Makefile
+++ b/userspace/units/pmu/Makefile
@@ -1,4 +1,4 @@
-# Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+# Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
 #
 # Permission is hereby granted, free of charge, to any person obtaining a
 # copy of this software and associated documentation files (the "Software"),
@@ -23,16 +23,11 @@
 OBJS   = nvgpu-pmu.o
 MODULE = nvgpu-pmu
 
-LIB_PATHS += -lfalcon_utf \
-	     -lmock-iospace
+LIB_PATHS += -lfalcon_utf
 
 include ../Makefile.units
 
-lib$(MODULE).so: falcon_utf \
-		 mock-iospace
+lib$(MODULE).so: falcon_utf
 
 falcon_utf:
 	$(MAKE) -C ../falcon
-
-mock-iospace:
-	$(MAKE) -C ../mock-iospace
diff --git a/userspace/units/pmu/Makefile.tmk b/userspace/units/pmu/Makefile.tmk
index 689fe0552..f1402b77c 100644
--- a/userspace/units/pmu/Makefile.tmk
+++ b/userspace/units/pmu/Makefile.tmk
@@ -28,8 +28,7 @@ NVGPU_UNIT_NAME=nvgpu-pmu
 NVGPU_UNIT_SRCS=nvgpu-pmu.c
 
 NVGPU_UNIT_INTERFACE_DIRS := \
-	$(NV_COMPONENT_DIR)/../falcon \
-	$(NV_COMPONENT_DIR)/../mock-iospace
+	$(NV_COMPONENT_DIR)/../falcon
 
 include $(NV_COMPONENT_DIR)/../Makefile.units.common.tmk
 
diff --git a/userspace/units/pmu/nvgpu-pmu.c b/userspace/units/pmu/nvgpu-pmu.c
index e2c1efc9e..2ad356363 100644
--- a/userspace/units/pmu/nvgpu-pmu.c
+++ b/userspace/units/pmu/nvgpu-pmu.c
@@ -20,19 +20,25 @@
  * DEALINGS IN THE SOFTWARE.
  */
 #include <stdlib.h>
+
 #include <unit/unit.h>
 #include <unit/io.h>
+
 #include <nvgpu/gk20a.h>
 #include <nvgpu/pmu.h>
 #include <nvgpu/falcon.h>
-#include <nvgpu/posix/io.h>
-#include <nvgpu/posix/posix-fault-injection.h>
 #include <nvgpu/hal_init.h>
-#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
-#include <nvgpu/hw/gk20a/hw_falcon_gk20a.h>
-#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
+
 #include <nvgpu/gr/gr.h>
+
+#include <nvgpu/posix/io.h>
+#include <nvgpu/posix/mock-regs.h>
 #include <nvgpu/posix/soc_fuse.h>
+#include <nvgpu/posix/posix-fault-injection.h>
+
+#include <nvgpu/hw/gk20a/hw_falcon_gk20a.h>
+#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
+#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
 
 #include "hal/fuse/fuse_gm20b.h"
@@ -40,81 +46,22 @@
 
 #include "../falcon/falcon_utf.h"
 #include "../gr/nvgpu-gr-gv11b.h"
-#include "../mock-iospace/include/gv11b_mock_regs.h"
 #include "nvgpu-pmu.h"
 
-#define NV_PMC_BOOT_0_ARCHITECTURE_GV110        (0x00000015 << \
-						NVGPU_GPU_ARCHITECTURE_SHIFT)
-#define NV_PMC_BOOT_0_IMPLEMENTATION_B          0xB
-
-#define NUM_REG_SPACES 10U
-
 struct utf_falcon *pmu_flcn;
 
-struct gr_test_reg_details {
-	int idx;
-	u32 base;
-	u32 size;
-	const u32 *data;
-};
-
-struct gr_test_reg_details gr_gv11b_reg_space[NUM_REG_SPACES] = {
-	[0] = {
-		.idx = gv11b_master_reg_idx,
-		.base = 0x00000000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[1] = {
-		.idx = gv11b_pri_reg_idx,
-		.base = 0x00120000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[2] = {
-		.idx = gv11b_fuse_reg_idx,
-		.base = 0x00021000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[3] = {
-		.idx = gv11b_top_reg_idx,
-		.base = 0x00022400,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[4] = {
-		.idx = gv11b_gr_reg_idx,
-		.base = 0x00400000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[5] = {
-		.idx = gv11b_fifo_reg_idx,
-		.base = 0x2000,
-		.size = 0x0,
-		.data = NULL,
-	},
-	[6] = { /* NV_FBIO_REGSPACE */
-		.base = 0x100800,
-		.size = 0x7FF,
-		.data = NULL,
-	},
-	[7] = { /* NV_PLTCG_LTCS_REGSPACE */
+#define NUM_REG_SPACES 2U
+static struct nvgpu_mock_iospace reg_spaces[NUM_REG_SPACES] = {
+	[0] = { /* NV_PLTCG_LTCS_REGSPACE */
 		.base = 0x17E200,
 		.size = 0x100,
 		.data = NULL,
 	},
-	[8] = { /* NV_PFB_HSHUB_ACTIVE_LTCS REGSPACE */
+	[1] = { /* NV_PFB_HSHUB_ACTIVE_LTCS REGSPACE */
 		.base = 0x1FBC20,
 		.size = 0x4,
 		.data = NULL,
 	},
-	[9] = { /* NV_PCCSR_CHANNEL REGSPACE */
-		.base = 0x800004,
-		.size = 0x1F,
-		.data = NULL,
-	},
 };
 
 
@@ -198,70 +145,30 @@ static void utf_falcon_register_io(struct gk20a *g)
 	nvgpu_posix_register_io(g, &utf_falcon_reg_callbacks);
 }
 
-static int gr_io_add_reg_space(struct unit_module *m, struct gk20a *g)
+static int add_reg_space(struct unit_module *m, struct gk20a *g)
 {
-	int ret = UNIT_SUCCESS;
-	u32 i = 0, j = 0;
-	u32 base, size;
-	struct nvgpu_posix_io_reg_space *gr_io_reg;
+	int err;
+	u32 i;
 
 	for (i = 0; i < NUM_REG_SPACES; i++) {
-		base = gr_gv11b_reg_space[i].base;
-		size = gr_gv11b_reg_space[i].size;
-		if (size == 0) {
-			struct mock_iospace iospace = {0};
+		struct nvgpu_mock_iospace *iospace = &reg_spaces[i];
 
-			ret = gv11b_get_mock_iospace(gr_gv11b_reg_space[i].idx,
-				&iospace);
-			if (ret != 0) {
-				unit_err(m, "failed to get reg space for %08x\n",
-					base);
-				goto clean_init_reg_space;
-			}
-			gr_gv11b_reg_space[i].data = iospace.data;
-			gr_gv11b_reg_space[i].size = size = iospace.size;
-		}
-		if (nvgpu_posix_io_add_reg_space(g, base, size) != 0) {
-			unit_err(m, "failed to add reg space for %08x\n", base);
-			ret = UNIT_FAIL;
-			goto clean_init_reg_space;
-		}
-
-		gr_io_reg = nvgpu_posix_io_get_reg_space(g, base);
-		if (gr_io_reg == NULL) {
-			unit_err(m, "failed to get reg space for %08x\n", base);
-			ret = UNIT_FAIL;
-			goto clean_init_reg_space;
-		}
-
-		if (gr_gv11b_reg_space[i].data != NULL) {
-			memcpy(gr_io_reg->data, gr_gv11b_reg_space[i].data, size);
-		} else {
-			memset(gr_io_reg->data, 0, size);
-		}
+		err = nvgpu_posix_io_add_reg_space(g, iospace->base,
+						   iospace->size);
+		nvgpu_assert(err == 0);
 	}
 
-	return ret;
-
-clean_init_reg_space:
-	for (j = 0; j < i; j++) {
-		base = gr_gv11b_reg_space[j].base;
-		nvgpu_posix_io_delete_reg_space(g, base);
-	}
-
-	return ret;
+	return 0;
 }
 
 static int init_pmu_falcon_test_env(struct unit_module *m, struct gk20a *g)
 {
 	int err = 0;
 
-	nvgpu_posix_io_init_reg_space(g);
-
 	/*
 	 * Initialise GR registers
 	 */
-	if (gr_io_add_reg_space(m, g) == UNIT_FAIL) {
+	if (add_reg_space(m, g) == UNIT_FAIL) {
 		unit_err(m, "failed to get initialized GR reg space\n");
 		return UNIT_FAIL;
 	}
@@ -278,10 +185,6 @@ static int init_pmu_falcon_test_env(struct unit_module *m, struct gk20a *g)
 		return -ENOMEM;
 	}
 
-	/* HAL init parameters for gv11b */
-	g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
-	g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
-
 	/* HAL init required for getting the falcon ops initialized. */
 	err = nvgpu_init_hal(g);
 	if (err != 0) {
@@ -787,8 +690,7 @@ static int free_falcon_test_env(struct unit_module *m, struct gk20a *g,
 	u32 i = 0;
 
 	for (i = 0; i < NUM_REG_SPACES; i++) {
-		u32 base = gr_gv11b_reg_space[i].base;
-		nvgpu_posix_io_delete_reg_space(g, base);
+		nvgpu_posix_io_delete_reg_space(g, reg_spaces[i].base);
 	}
 
 	nvgpu_utf_falcon_free(g, pmu_flcn);
diff --git a/userspace/units/posix/mockio/Makefile b/userspace/units/posix/mockio/Makefile
deleted file mode 100644
index aeb5e623e..000000000
--- a/userspace/units/posix/mockio/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-.SUFFIXES:
-
-OBJS   = posix-mockio.o
-MODULE = posix-mockio
-
-include ../../Makefile.units
diff --git a/userspace/units/posix/mockio/Makefile.interface.tmk b/userspace/units/posix/mockio/Makefile.interface.tmk
deleted file mode 100644
index f7b4cee43..000000000
--- a/userspace/units/posix/mockio/Makefile.interface.tmk
+++ /dev/null
@@ -1,35 +0,0 @@
-################################### tell Emacs this is a -*- makefile-gmake -*-
-#
-# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-#
-# tmake for SW Mobile component makefile
-#
-###############################################################################
-
-NVGPU_UNIT_NAME=posix-mockio
-
-include $(NV_COMPONENT_DIR)/../../Makefile.units.common.interface.tmk
-
-# Local Variables:
-# indent-tabs-mode: t
-# tab-width: 8
-# End:
-# vi: set tabstop=8 noexpandtab:
diff --git a/userspace/units/posix/mockio/Makefile.tmk b/userspace/units/posix/mockio/Makefile.tmk
deleted file mode 100644
index dfc548762..000000000
--- a/userspace/units/posix/mockio/Makefile.tmk
+++ /dev/null
@@ -1,35 +0,0 @@
-################################### tell Emacs this is a -*- makefile-gmake -*-
-#
-# Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included in
-# all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-#
-# tmake for SW Mobile component makefile
-#
-###############################################################################
-
-NVGPU_UNIT_NAME=posix-mockio
-
-include $(NV_COMPONENT_DIR)/../../Makefile.units.common.tmk
-
-# Local Variables:
-# indent-tabs-mode: t
-# tab-width: 8
-# End:
-# vi: set tabstop=8 noexpandtab:
diff --git a/userspace/units/posix/mockio/posix-mockio.c b/userspace/units/posix/mockio/posix-mockio.c
deleted file mode 100644
index 892d60a14..000000000
--- a/userspace/units/posix/mockio/posix-mockio.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*
- * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#include <stdlib.h>
-
-#include <unit/io.h>
-#include <unit/unit.h>
-
-#include <nvgpu/io.h>
-#include <nvgpu/io_usermode.h>
-#include <nvgpu/posix/io.h>
-
-struct writel_test_args {
-	const char *name;
-	void (*fn)(struct gk20a *, u32, u32);
-};
-
-struct readl_test_args {
-	const char *name;
-	u32 (*fn)(struct gk20a *, u32);
-};
-
-/**
- * This is both a very simple functional test and documentation for how to use
- * the core IO mocking API.
- *
- * The testing is very simple: just generate a bunch of reads and writes and
- * check that they make it to the call back functions correctly.
- */
-
-static struct nvgpu_reg_access mockio_access;
-
-/*
- * List of writes to test with.
- */
-static struct nvgpu_reg_access test_access_list[] = {
-	{ 0U,		0U },
-	{ ~0U,		~0U },
-	{ 0x100U,	0x30U },
-	{ 0x0U,		0x100U },
-	{ 0x1000000U,	0x0U },
-	{ 0xFFU,	0xFFU },
-	{ 0x1U,		0x1U },
-	{ 0x10U,	0x30U },
-};
-
-/*
- * The *writel*() access functions copy the incoming write into our own
- * access info. That way one can do the following:
- *
- *   nvgpu_writel(g, reg, val);
- *
- * And then:
- *
- *   do_something_with(writel_access.addr, writel_access.value);
- *
- * No bounds checking is performed by the mock API so that's up to you.
- * Higher level APIs may do this.
- */
-static void writel_access_fn(struct gk20a *g,
-			     struct nvgpu_reg_access *access)
-{
-	memcpy(&mockio_access, access, sizeof(mockio_access));
-}
-
-/*
- * Reads are handled by simply passing back a value. Exactly the opposite as the
- * write APIs.
- */
-static void readl_access_fn(struct gk20a *g,
-			    struct nvgpu_reg_access *access)
-{
-	/*
-	 * The mock API checks that the returned address is actually the same as
-	 * the requested address. If it mismatches then the mock IO API returns
-	 * 0x0 to the nvgpu caller.
-	 */
-	memcpy(access, &mockio_access, sizeof(mockio_access));
-}
-
-static struct nvgpu_posix_io_callbacks test_callbacks = {
-	/* Write APIs all can use the same accessor. */
-	.writel          = writel_access_fn,
-	.writel_check    = writel_access_fn,
-	.bar1_writel     = writel_access_fn,
-	.usermode_writel = writel_access_fn,
-
-	/* Likewise for the read APIs. */
-	.__readl         = readl_access_fn,
-	.readl           = readl_access_fn,
-	.bar1_readl      = readl_access_fn,
-};
-
-static int test_register_io_callbacks(struct unit_module *m, struct gk20a *g,
-				      void *__args)
-{
-	nvgpu_posix_register_io(g, &test_callbacks);
-
-	return UNIT_SUCCESS;
-}
-
-static int test_writel(struct unit_module *m, struct gk20a *g, void *__args)
-{
-	unsigned int i;
-	struct nvgpu_reg_access *a;
-	struct writel_test_args *args = __args;
-
-	for (i = 0;
-	     i < sizeof(test_access_list) / sizeof(test_access_list[0]);
-	     i++) {
-		a = &test_access_list[i];
-
-		memset(&mockio_access, 0, sizeof(mockio_access));
-
-		args->fn(g, a->addr, a->value);
-
-		if (mockio_access.addr != a->addr ||
-		    mockio_access.value != a->value) {
-			unit_return_fail(m, "%s() mismatch!\n", args->name);
-		}
-	}
-
-	return UNIT_SUCCESS;
-}
-
-static int test_readl(struct unit_module *m, struct gk20a *g, void *__args)
-{
-	unsigned int i;
-	struct nvgpu_reg_access *a;
-	struct readl_test_args *args = __args;
-
-	for (i = 0;
-	     i < sizeof(test_access_list) / sizeof(test_access_list[0]);
-	     i++) {
-		u32 ret;
-
-		a = &test_access_list[i];
-		memcpy(&mockio_access, a, sizeof(mockio_access));
-
-		ret = args->fn(g, a->value);
-
-		if (ret != a->value) {
-			unit_return_fail(m, "%s() mismatch!\n", args->name);
-		}
-	}
-
-	return UNIT_SUCCESS;
-}
-
-struct writel_test_args nvgpu_writel_args = {
-	.name = "nvgpu_writel",
-	.fn   = nvgpu_writel
-};
-
-struct writel_test_args nvgpu_writel_check_args = {
-	.name = "nvgpu_writel_check",
-	.fn   = nvgpu_writel_check
-};
-
-struct writel_test_args nvgpu_bar1_writel_args = {
-	.name = "nvgpu_bar1_writel",
-	.fn   = nvgpu_bar1_writel
-};
-
-struct writel_test_args nvgpu_usermode_writel_args = {
-	.name = "nvgpu_usermode_writel",
-	.fn   = nvgpu_usermode_writel
-};
-
-struct readl_test_args nvgpu_readl_args = {
-	.name = "nvgpu_readl",
-	.fn   = nvgpu_readl
-};
-
-struct readl_test_args nvgpu_readl_impl_args = {
-	.name = "nvgpu_readl_impl",
-	.fn   = nvgpu_readl_impl
-};
-
-struct readl_test_args nvgpu_bar1_readl_args = {
-	.name = "nvgpu_bar1_readl",
-	.fn   = nvgpu_bar1_readl
-};
-
-/*
- * Typical example of a write callback. At the very least the callback
- * should forward the write access to the mock IO framework and also
- * call the API to record transactions. This function would be a great
- * place to add test logic to run at every register write.
- */
-static void writel_access_reg_fn(struct gk20a *g,
-			     struct nvgpu_reg_access *access)
-{
-	nvgpu_posix_io_writel_reg_space(g, access->addr, access->value);
-	nvgpu_posix_io_record_access(g, access);
-}
-
-/*
- * Example of a read callback. At the very least the callback should
- * get the register value from the mock IO framework. You could also add
- * some test logic to run at every register read.
- */
-static void readl_access_reg_fn(struct gk20a *g,
-			    struct nvgpu_reg_access *access)
-{
-	access->value = nvgpu_posix_io_readl_reg_space(g, access->addr);
-}
-
-/*
- * Define all the callbacks to be used during the test. Typically all
- * write operations use the same callback, likewise for all read operations.
- */
-static struct nvgpu_posix_io_callbacks test_reg_callbacks = {
-	/* Write APIs all can use the same accessor. */
-	.writel          = writel_access_reg_fn,
-	.writel_check    = writel_access_reg_fn,
-	.bar1_writel     = writel_access_reg_fn,
-	.usermode_writel = writel_access_reg_fn,
-
-	/* Likewise for the read APIs. */
-	.__readl         = readl_access_reg_fn,
-	.readl           = readl_access_reg_fn,
-	.bar1_readl      = readl_access_reg_fn,
-};
-
-static int test_register_space(struct unit_module *m, struct gk20a *g,
-				void *__args)
-{
-	u32 value;
-
-	nvgpu_posix_io_init_reg_space(g);
-	nvgpu_posix_io_start_recorder(g);
-
-	/* Define a couple of register spaces */
-	if (nvgpu_posix_io_add_reg_space(g, 0x10000000, 0x100) != 0) {
-		return UNIT_FAIL;
-	}
-	if (nvgpu_posix_io_add_reg_space(g, 0x80000000, 0x1000) != 0) {
-		return UNIT_FAIL;
-	}
-
-	/*
-	 * Some direct access operations to test register IO. This could be
-	 * used to initialize memory before starting the actual test.
-	 */
-	nvgpu_posix_io_writel_reg_space(g, 0x10000000, 0x12345678);
-	nvgpu_posix_io_writel_reg_space(g, 0x80000004, 0x87654321);
-	value = nvgpu_posix_io_readl_reg_space(g, 0x80000004);
-	if (value != 0x87654321) {
-		return UNIT_FAIL;
-	}
-	nvgpu_posix_io_writel_reg_space(g, 0x100000FC, 0x2727);
-
-	/* Now re-define the callbacks to perform our own testing */
-	struct nvgpu_posix_io_callbacks *old_cbs = nvgpu_posix_register_io(g,
-		&test_reg_callbacks);
-
-	/* The test begins where we would call some real NVGPU code */
-	nvgpu_writel(g, 0x80000008, 0xA1B1C1D1);
-	nvgpu_writel(g, 0x1000000C, 0x1);
-	nvgpu_writel(g, 0x10000010, 0x55);
-	/* End of real NVGPU code */
-
-	/* First check that no memory access error occurred */
-	if (nvgpu_posix_io_get_error_code(g) != 0) {
-		unit_return_fail(m, "IO Access Error\n");
-	}
-
-	/* Verification can then be done either using nvgpu_readl or
-	 * nvgpu_posix_io_readl_reg_space
-	 */
-	value = nvgpu_readl(g, 0x80000008);
-	if (value != 0xA1B1C1D1) {
-		unit_return_fail(m, "Register value mismatch at address=0x%x\n",
-			0x80000008);
-	}
-
-	/* Define a sequence of expected register writes */
-	struct nvgpu_reg_access sequence[] = {
-		{ .addr = 0x80000008, .value = 0xA1B1C1D1 },
-		{ .addr = 0x1000000C, .value = 0x1 },
-		{ .addr = 0x10000010, .value = 0x55 }
-	};
-
-	/* Compare the recording with the expected sequence. If strict mode is
-	 * used, then the same accesses, order and number of accesses is
-	 * expected.
-	 */
-	if (nvgpu_posix_io_check_sequence(g, sequence,
-		sizeof(sequence)/sizeof(struct nvgpu_reg_access),
-		true) == false) {
-		unit_return_fail(m, "Failed checking sequence\n");
-	}
-
-	/* Calling this function again resets the recorder to use it again */
-	nvgpu_posix_io_start_recorder(g);
-
-	/* Free the reg space structures, too */
-	nvgpu_posix_io_delete_reg_space(g, 0x10000000);
-	nvgpu_posix_io_delete_reg_space(g, 0x80000000);
-
-	/* Restore the old callbacks for other tests within this unit */
-	nvgpu_posix_register_io(g, old_cbs);
-
-	return UNIT_SUCCESS;
-}
-
-
-struct unit_module_test posix_mockio_tests[] = {
-	UNIT_TEST(register_io_callbacks, test_register_io_callbacks, NULL, 0),
-	UNIT_TEST(writel,		 test_writel, &nvgpu_writel_args, 0),
-	UNIT_TEST(writel_check,		 test_writel, &nvgpu_writel_check_args, 0),
-	UNIT_TEST(bar1_writel,		 test_writel, &nvgpu_bar1_writel_args, 0),
-	UNIT_TEST(usermode_writel,	 test_writel,
-		  &nvgpu_usermode_writel_args, 0),
-	UNIT_TEST(readl,		 test_readl, &nvgpu_readl_args, 0),
-	UNIT_TEST(readl_impl,		 test_readl, &nvgpu_readl_impl_args, 0),
-	UNIT_TEST(bar1_readl,		 test_readl, &nvgpu_bar1_readl_args, 0),
-	UNIT_TEST(test_register_space,	 test_register_space, NULL, 0),
-};
-
-UNIT_MODULE(posix_mockio, posix_mockio_tests, UNIT_PRIO_POSIX_TEST);
-
diff --git a/userspace/units/pramin/nvgpu-pramin.c b/userspace/units/pramin/nvgpu-pramin.c
index a6ca38787..52e935a44 100644
--- a/userspace/units/pramin/nvgpu-pramin.c
+++ b/userspace/units/pramin/nvgpu-pramin.c
@@ -188,7 +188,6 @@ static int init_test_env(struct unit_module *m, struct gk20a *g)
 	}
 
 	nvgpu_posix_register_io(g, &pramin_callbacks);
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Minimum HAL init for PRAMIN */
 	g->ops.bus.set_bar0_window = gk20a_bus_set_bar0_window;
diff --git a/userspace/units/priv_ring/nvgpu-priv_ring.c b/userspace/units/priv_ring/nvgpu-priv_ring.c
index 3e8db914e..60512340b 100644
--- a/userspace/units/priv_ring/nvgpu-priv_ring.c
+++ b/userspace/units/priv_ring/nvgpu-priv_ring.c
@@ -123,8 +123,6 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.get_litter_value = gv11b_get_litter_value;
 	g->ops.mc.intr_stall_unit_config =
 					mc_gp10b_intr_stall_unit_config;
-	/* Init register space */
-	nvgpu_posix_io_init_reg_space(g);
 
 	/* Map register space NV_PRIV_MASTER */
 	if (nvgpu_posix_io_add_reg_space(g, NV_PRIV_MASTER_START,
diff --git a/userspace/units/ptimer/nvgpu-ptimer.c b/userspace/units/ptimer/nvgpu-ptimer.c
index ebcba60f7..0c16402aa 100644
--- a/userspace/units/ptimer/nvgpu-ptimer.c
+++ b/userspace/units/ptimer/nvgpu-ptimer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -89,7 +89,6 @@ int test_setup_env(struct unit_module *m,
 	g->ops.ptimer.isr = gk20a_ptimer_isr;
 
 	/* Create ptimer register space */
-	nvgpu_posix_io_init_reg_space(g);
 	if (nvgpu_posix_io_add_reg_space(g, PTIMER_REG_SPACE_START,
 					 PTIMER_REG_SPACE_SIZE) != 0) {
 		unit_err(m, "%s: failed to create register space\n",
diff --git a/userspace/units/rc/nvgpu-rc.c b/userspace/units/rc/nvgpu-rc.c
index cd39ec434..76298fe6e 100644
--- a/userspace/units/rc/nvgpu-rc.c
+++ b/userspace/units/rc/nvgpu-rc.c
@@ -88,48 +88,22 @@ int test_rc_init(struct unit_module *m, struct gk20a *g, void *args)
 		unit_return_fail(m, "fifo reg_space failure");
 	}
 
-	/*
-	 * HAL init parameters for gv11b
-	 */
-	g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
-	g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
-
-	/*
-	 * HAL init required for getting
-	 * the sync ops initialized.
-	 */
-	ret = nvgpu_init_hal(g);
-	if (ret != 0) {
-		unit_err(m, "failed to init hal");
-		goto clean_regspace;
-	}
-
 	g->ops.gr.init.get_no_of_sm = stub_gv11b_gr_init_get_no_of_sm;
 
 	g->ops.ecc.ecc_init_support(g);
 	g->ops.mm.init_mm_support(g);
 
 	ret = nvgpu_fifo_init_support(g);
-	if (ret != 0) {
-		unit_err(m , "failed to init fifo support");
-		goto clean_regspace;
-	}
+	nvgpu_assert(ret == 0);
 
 	/* Do not allocate from vidmem */
 	nvgpu_set_enabled(g, NVGPU_MM_UNIFIED_MEMORY, true);
 
 	ret = nvgpu_runlist_setup_sw(g);
-	if (ret != 0) {
-		unit_err(m, "failed runlist setup_sw");
-		goto clean_regspace;
-	}
+	nvgpu_assert(ret == 0);
 
 	tsg = nvgpu_tsg_open(g, getpid());
-	if (tsg == NULL) {
-		ret = UNIT_FAIL;
-		unit_err(m, "failed tsg open");
-		goto clean_regspace;
-	}
+	nvgpu_assert(tsg != NULL);
 
 	ch = nvgpu_channel_open_new(g, NVGPU_INVALID_RUNLIST_ID, false,
 			getpid(), getpid());
@@ -163,8 +137,6 @@ clear_channel:
 clear_tsg:
 	nvgpu_ref_put(&tsg->refcount, nvgpu_tsg_release);
 	tsg = NULL;
-clean_regspace:
-	test_fifo_cleanup_gv11b_reg_space(m, g);
 
 	return ret;
 }
@@ -194,8 +166,6 @@ int test_rc_deinit(struct unit_module *m, struct gk20a *g, void *args)
 		g->fifo.remove_support(&g->fifo);
 	}
 
-	test_fifo_cleanup_gv11b_reg_space(m, g);
-
 	return ret;
 }
 
@@ -473,4 +443,4 @@ struct unit_module_test nvgpu_rc_tests[] = {
 	UNIT_TEST(rc_deinit, test_rc_deinit, NULL, 0),
 };
 
-UNIT_MODULE(nvgpu-rc, nvgpu_rc_tests, UNIT_PRIO_NVGPU_TEST);
\ No newline at end of file
+UNIT_MODULE(nvgpu-rc, nvgpu_rc_tests, UNIT_PRIO_NVGPU_TEST);
diff --git a/userspace/units/sync/nvgpu-sync.c b/userspace/units/sync/nvgpu-sync.c
index 7eda9e1f0..835008de9 100644
--- a/userspace/units/sync/nvgpu-sync.c
+++ b/userspace/units/sync/nvgpu-sync.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -110,12 +110,6 @@ int test_sync_init(struct unit_module *m, struct gk20a *g, void *args)
 
 	nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, true);
 
-	/*
-	 * HAL init parameters for gv11b
-	 */
-	g->params.gpu_arch = NV_PMC_BOOT_0_ARCHITECTURE_GV110;
-	g->params.gpu_impl = NV_PMC_BOOT_0_IMPLEMENTATION_B;
-
 	/*
 	 * HAL init required for getting
 	 * the sync ops initialized.
@@ -546,8 +540,6 @@ int test_sync_deinit(struct unit_module *m, struct gk20a *g, void *args)
 
 	nvgpu_free_nvhost_dev(g);
 
-	test_fifo_cleanup_gv11b_reg_space(m, g);
-
 	return UNIT_SUCCESS;
 }
 
diff --git a/userspace/units/therm/nvgpu-therm.c b/userspace/units/therm/nvgpu-therm.c
index 5d7d73b65..703265b8b 100644
--- a/userspace/units/therm/nvgpu-therm.c
+++ b/userspace/units/therm/nvgpu-therm.c
@@ -77,7 +77,6 @@ int test_setup_env(struct unit_module *m,
 			  struct gk20a *g, void *args)
 {
 	/* Create therm register space */
-	nvgpu_posix_io_init_reg_space(g);
 	if (nvgpu_posix_io_add_reg_space(g, THERM_ADDR_SPACE_START,
 						THERM_ADDR_SPACE_SIZE) != 0) {
 		unit_err(m, "%s: failed to create register space\n",
diff --git a/userspace/units/top/nvgpu-top.c b/userspace/units/top/nvgpu-top.c
index f0266b4cd..3c0dbc1aa 100644
--- a/userspace/units/top/nvgpu-top.c
+++ b/userspace/units/top/nvgpu-top.c
@@ -90,9 +90,6 @@ int test_top_setup(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.top.get_num_ltcs = gm20b_top_get_num_ltcs;
 	g->ops.top.get_num_lce = gv11b_top_get_num_lce;
 
-	/* Init register space */
-	nvgpu_posix_io_init_reg_space(g);
-
 	/* Map register space NV_TOP */
 	if (nvgpu_posix_io_add_reg_space(g, NV_TOP_START, NV_TOP_SIZE) != 0) {
 		unit_err(m, "%s: failed to register space: NV_TOP\n",