mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
Revert "gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client"
This reverts commit 57821e2157.
Change-Id: Ic4801115064ccbcd1435298a61871921d056b8ea
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/1247825
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Babu Bodla <rbodla@nvidia.com>
This commit is contained in:
committed by
Rakesh Babu Bodla
parent
57821e2157
commit
5f1c2bc27f
@@ -110,6 +110,7 @@ struct zcull_ctx_desc {
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struct pm_ctx_desc {
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struct pm_ctx_desc {
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struct mem_desc mem;
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struct mem_desc mem;
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u32 pm_mode;
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u32 pm_mode;
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bool ctx_was_enabled; /* Used in the virtual case only */
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};
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};
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struct gk20a;
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struct gk20a;
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@@ -91,10 +91,8 @@ int vgpu_gr_init_ctx_state(struct gk20a *g)
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g->gr.ctx_vars.golden_image_size = priv->constants.golden_ctx_size;
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g->gr.ctx_vars.golden_image_size = priv->constants.golden_ctx_size;
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g->gr.ctx_vars.zcull_ctxsw_image_size = priv->constants.zcull_ctx_size;
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g->gr.ctx_vars.zcull_ctxsw_image_size = priv->constants.zcull_ctx_size;
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g->gr.ctx_vars.pm_ctxsw_image_size = priv->constants.hwpm_ctx_size;
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if (!g->gr.ctx_vars.golden_image_size ||
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if (!g->gr.ctx_vars.golden_image_size ||
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!g->gr.ctx_vars.zcull_ctxsw_image_size ||
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!g->gr.ctx_vars.zcull_ctxsw_image_size)
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!g->gr.ctx_vars.pm_ctxsw_image_size)
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return -ENXIO;
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return -ENXIO;
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gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size;
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gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size;
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@@ -392,13 +390,12 @@ static void vgpu_gr_free_channel_pm_ctx(struct channel_gk20a *c)
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_channel_free_hwpm_ctx *p = &msg.params.free_hwpm_ctx;
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struct tegra_vgpu_channel_free_hwpm_ctx *p = &msg.params.free_hwpm_ctx;
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struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
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struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
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struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx;
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int err;
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int err;
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gk20a_dbg_fn("");
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gk20a_dbg_fn("");
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/* check if hwpm was ever initialized. If not, nothing to do */
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/* check if hwpm was ever initialized. If not, nothing to do */
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if (pm_ctx->mem.gpu_va == 0)
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if (ch_ctx->pm_ctx.ctx_was_enabled == false)
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return;
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return;
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msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX;
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msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX;
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@@ -407,8 +404,7 @@ static void vgpu_gr_free_channel_pm_ctx(struct channel_gk20a *c)
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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WARN_ON(err || msg.ret);
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WARN_ON(err || msg.ret);
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gk20a_vm_free_va(c->vm, pm_ctx->mem.gpu_va, pm_ctx->mem.size, 0);
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ch_ctx->pm_ctx.ctx_was_enabled = false;
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pm_ctx->mem.gpu_va = 0;
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}
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}
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static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c)
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static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c)
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@@ -1044,34 +1040,27 @@ static int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
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static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
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static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
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struct channel_gk20a *ch, bool enable)
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struct channel_gk20a *ch, bool enable)
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{
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{
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struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
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struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx;
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode;
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struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode;
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int err;
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int err;
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gk20a_dbg_fn("");
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gk20a_dbg_fn("");
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if (enable) {
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p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW;
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/* Allocate buffer if necessary */
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if (pm_ctx->mem.gpu_va == 0) {
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pm_ctx->mem.gpu_va = gk20a_vm_alloc_va(ch->vm,
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g->gr.ctx_vars.pm_ctxsw_image_size,
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gmmu_page_size_kernel);
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if (!pm_ctx->mem.gpu_va)
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return -ENOMEM;
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pm_ctx->mem.size = g->gr.ctx_vars.pm_ctxsw_image_size;
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}
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} else
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p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW;
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msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE;
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msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE;
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msg.handle = vgpu_get_handle(g);
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msg.handle = vgpu_get_handle(g);
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p->handle = ch->virt_ctx;
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p->handle = ch->virt_ctx;
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p->gpu_va = pm_ctx->mem.gpu_va;
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/* If we just enabled HWPM context switching, flag this
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* so we know we need to free the buffer when channel contexts
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* are cleaned up.
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*/
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if (enable) {
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struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
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ch_ctx->pm_ctx.ctx_was_enabled = true;
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p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW;
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} else
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p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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WARN_ON(err || msg.ret);
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WARN_ON(err || msg.ret);
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@@ -348,7 +348,6 @@ enum {
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struct tegra_vgpu_channel_set_ctxsw_mode {
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struct tegra_vgpu_channel_set_ctxsw_mode {
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u64 handle;
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u64 handle;
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u64 gpu_va;
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u32 mode;
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u32 mode;
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};
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};
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@@ -437,7 +436,6 @@ struct tegra_vgpu_constants_params {
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* TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC
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* TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC
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*/
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*/
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u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT];
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u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT];
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u32 hwpm_ctx_size;
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};
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};
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struct tegra_vgpu_channel_cyclestats_snapshot_params {
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struct tegra_vgpu_channel_cyclestats_snapshot_params {
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