diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
index 5fc9dcaea..7339ed7b3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
@@ -70,6 +70,7 @@
 #define pgsp_falcon_irqstat_exterr_true_f()                              (0x20U)
 #define pgsp_falcon_irqstat_swgen0_true_f()                              (0x40U)
 #define pgsp_falcon_irqstat_swgen1_true_f()                              (0x80U)
+#define pgsp_falcon_irqsclr_r()                                    (0x00110004U)
 #define pgsp_falcon_irqmode_r()                                    (0x0011000cU)
 #define pgsp_riscv_irqmset_r()                                     (0x00111520U)
 #define pgsp_riscv_irqmset_gptmr_f(v)                    ((U32(v) & 0x1U) << 0U)
@@ -101,6 +102,46 @@
 #define pgsp_riscv_irqdest_swgen0_f(v)                   ((U32(v) & 0x1U) << 6U)
 #define pgsp_riscv_irqdest_swgen1_f(v)                   ((U32(v) & 0x1U) << 7U)
 #define pgsp_riscv_irqdest_ext_f(v)                     ((U32(v) & 0xffU) << 8U)
+#define pgsp_fbif_transcfg_r(i)\
+		(nvgpu_safe_add_u32(0x00110600U, nvgpu_safe_mult_u32((i), 4U)))
+#define pgsp_fbif_transcfg_target_local_fb_f()                            (0x0U)
+#define pgsp_fbif_transcfg_target_coherent_sysmem_f()                     (0x1U)
+#define pgsp_fbif_transcfg_target_noncoherent_sysmem_f()                  (0x2U)
+#define pgsp_fbif_transcfg_mem_type_s()                                     (1U)
+#define pgsp_fbif_transcfg_mem_type_f(v)                 ((U32(v) & 0x1U) << 2U)
+#define pgsp_fbif_transcfg_mem_type_m()                        (U32(0x1U) << 2U)
+#define pgsp_fbif_transcfg_mem_type_v(r)                    (((r) >> 2U) & 0x1U)
+#define pgsp_fbif_transcfg_mem_type_virtual_f()                           (0x0U)
+#define pgsp_fbif_transcfg_mem_type_physical_f()                          (0x4U)
+#define pgsp_hwcfg_r()                                             (0x00110abcU)
+#define pgsp_hwcfg_emem_size_f(v)                      ((U32(v) & 0x1ffU) << 0U)
+#define pgsp_hwcfg_emem_size_m()                             (U32(0x1ffU) << 0U)
+#define pgsp_hwcfg_emem_size_v(r)                         (((r) >> 0U) & 0x1ffU)
+#define pgsp_falcon_hwcfg1_r()                                     (0x0011012cU)
+#define pgsp_falcon_hwcfg1_dmem_tag_width_f(v)         ((U32(v) & 0x1fU) << 21U)
+#define pgsp_falcon_hwcfg1_dmem_tag_width_m()                (U32(0x1fU) << 21U)
+#define pgsp_falcon_hwcfg1_dmem_tag_width_v(r)            (((r) >> 21U) & 0x1fU)
+#define pgsp_ememc_r(i)\
+		(nvgpu_safe_add_u32(0x00110ac0U, nvgpu_safe_mult_u32((i), 8U)))
+#define pgsp_ememc__size_1_v()                                     (0x00000004U)
+#define pgsp_ememc_blk_f(v)                             ((U32(v) & 0xffU) << 8U)
+#define pgsp_ememc_blk_m()                                    (U32(0xffU) << 8U)
+#define pgsp_ememc_blk_v(r)                                (((r) >> 8U) & 0xffU)
+#define pgsp_ememc_offs_f(v)                            ((U32(v) & 0x3fU) << 2U)
+#define pgsp_ememc_offs_m()                                   (U32(0x3fU) << 2U)
+#define pgsp_ememc_offs_v(r)                               (((r) >> 2U) & 0x3fU)
+#define pgsp_ememc_aincw_f(v)                           ((U32(v) & 0x1U) << 24U)
+#define pgsp_ememc_aincw_m()                                  (U32(0x1U) << 24U)
+#define pgsp_ememc_aincw_v(r)                              (((r) >> 24U) & 0x1U)
+#define pgsp_ememc_aincr_f(v)                           ((U32(v) & 0x1U) << 25U)
+#define pgsp_ememc_aincr_m()                                  (U32(0x1U) << 25U)
+#define pgsp_ememc_aincr_v(r)                              (((r) >> 25U) & 0x1U)
+#define pgsp_ememd_r(i)\
+		(nvgpu_safe_add_u32(0x00110ac4U, nvgpu_safe_mult_u32((i), 8U)))
+#define pgsp_ememd__size_1_v()                                     (0x00000004U)
+#define pgsp_ememd_data_f(v)                      ((U32(v) & 0xffffffffU) << 0U)
+#define pgsp_ememd_data_m()                             (U32(0xffffffffU) << 0U)
+#define pgsp_ememd_data_v(r)                         (((r) >> 0U) & 0xffffffffU)
 #define pgsp_queue_head_r(i)\
 		(nvgpu_safe_add_u32(0x00110c00U, nvgpu_safe_mult_u32((i), 8U)))
 #define pgsp_queue_head__size_1_v()                                (0x00000008U)
@@ -111,4 +152,19 @@
 #define pgsp_queue_tail__size_1_v()                                (0x00000008U)
 #define pgsp_queue_tail_address_f(v)              ((U32(v) & 0xffffffffU) << 0U)
 #define pgsp_queue_tail_address_v(r)                 (((r) >> 0U) & 0xffffffffU)
+#define pgsp_msgq_head_r(i)\
+		(nvgpu_safe_add_u32(0x00110c80U, nvgpu_safe_mult_u32((i), 8U)))
+#define pgsp_msgq_head__size_1_v()                                 (0x00000008U)
+#define pgsp_msgq_head_val_f(v)                   ((U32(v) & 0xffffffffU) << 0U)
+#define pgsp_msgq_head_val_v(r)                      (((r) >> 0U) & 0xffffffffU)
+#define pgsp_msgq_tail_r(i)\
+		(nvgpu_safe_add_u32(0x00110c84U, nvgpu_safe_mult_u32((i), 8U)))
+#define pgsp_msgq_tail__size_1_v()                                 (0x00000008U)
+#define pgsp_msgq_tail_val_f(v)                   ((U32(v) & 0xffffffffU) << 0U)
+#define pgsp_msgq_tail_val_v(r)                      (((r) >> 0U) & 0xffffffffU)
+#define pgsp_falcon_exterraddr_r()                                 (0x00110168U)
+#define pgsp_falcon_exterrstat_r()                                 (0x0011016cU)
+#define pgsp_falcon_exterrstat_valid_m()                      (U32(0x1U) << 31U)
+#define pgsp_falcon_exterrstat_valid_v(r)                  (((r) >> 31U) & 0x1U)
+#define pgsp_falcon_exterrstat_valid_true_v()                      (0x00000001U)
 #endif