From 5f9cd1bca53a7b8414fc7cd210c71a06b80bb31a Mon Sep 17 00:00:00 2001 From: David Ung Date: Mon, 27 Apr 2020 16:15:59 -0700 Subject: [PATCH] gpu: nvgpu: Regenerated headers Regenerating header from register generator Bug 2833620 Change-Id: Idc8e922bb611ed5acae66b6ca38db4bb9c8a1904 Signed-off-by: David Ung Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335263 (cherry picked from commit dfab7cc86acdc26c3705551740c55b4d4898587a) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2351900 GVS: Gerrit_Virtual_Submit Tested-by: Amulya Yarlagadda Reviewed-by: Amulya Yarlagadda Reviewed-by: automaticguardword Reviewed-by: Automatic_Commit_Validation_User --- .../gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h | 4 ++-- .../nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h | 6 +++++- .../gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h | 4 ++-- .../nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h | 6 +++++- .../gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h | 8 ++++---- .../gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h | 4 ++-- .../nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 6 +++++- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 10 +++++----- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 4 ++-- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 4 ++-- 10 files changed, 34 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h index 28457634e..cf60ae51c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -706,7 +706,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) } static inline u32 pwr_pmu_idle_intr_status_intr_m(void) { - return U32(0x1U) << 0U; + return 0x1U << 0U; } static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h index b60dfc36c..6b5632a65 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -116,6 +116,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { return 0x7U << 0U; } +static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) +{ + return 0x1U; +} static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { return 0x0U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h index 2ca1f02bd..7b339ae57 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -750,7 +750,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) } static inline u32 pwr_pmu_idle_intr_status_intr_m(void) { - return U32(0x1U) << 0U; + return 0x1U << 0U; } static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h index b214bdb32..d83320fe7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -104,6 +104,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { return 0x7U << 0U; } +static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) +{ + return 0x1U; +} static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { return 0x0U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h index 07f39943e..6aeb43559 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gmmu_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -86,7 +86,7 @@ static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xfffffffU) << 8U; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pde_address_sys_w(void) { @@ -194,7 +194,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xfffffffU) << 8U; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { @@ -242,7 +242,7 @@ static inline u32 gmmu_new_pte_privilege_false_f(void) } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xfffffffU) << 8U; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_sys_w(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h index c160e8976..75f1c0469 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -754,7 +754,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) } static inline u32 pwr_pmu_idle_intr_status_intr_m(void) { - return U32(0x1U) << 0U; + return 0x1U << 0U; } static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index aa8e6190c..8b095b1a5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -140,6 +140,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { return 0x7U << 0U; } +static inline u32 ctxsw_prog_main_image_pm_mode_ctxsw_f(void) +{ + return 0x1U; +} static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { return 0x0U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index fe35bb711..767fc5a08 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -62,7 +62,7 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void) } static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void) { - return U32(0x1U) << 25U; + return 0x1U << 25U; } static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) { @@ -70,7 +70,7 @@ static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void) } static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_m(void) { - return U32(0x1U) << 26U; + return 0x1U << 26U; } static inline u32 fb_fbhub_num_active_ltcs_hub_sys_ncoh_atomic_mode_use_read_f(void) { @@ -94,7 +94,7 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) } static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void) { - return U32(0x3U) << 24U; + return 0x3U << 24U; } static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void) { @@ -106,7 +106,7 @@ static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void) } static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) { - return U32(0x1U) << 27U; + return 0x1U << 27U; } static inline u32 fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f(void) { @@ -118,7 +118,7 @@ static inline u32 fb_hshub_num_active_ltcs_r(void) } static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void) { - return U32(0x1U) << 25U; + return 0x1U << 25U; } static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 01dc99d58..f7d8089d8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -4978,11 +4978,11 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) } static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(void) { - return U32(0x3U) << 24U; + return 0x3U << 24U; } static inline u32 gr_gpcs_pri_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(void) { - return U32(0x1U) << 27U; + return 0x1U << 27U; } static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 295c6e957..03affe8e6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -914,7 +914,7 @@ static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v) } static inline u32 pwr_pmu_idle_intr_status_intr_m(void) { - return U32(0x1U) << 0U; + return 0x1U << 0U; } static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r) {