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Revert "gpu: nvgpu: get PMU NEXT core irqmask"

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This reverts commit 4ff427c51619cecdcc74fdbb388d82421cf45655.

Reason for revert: Testing for regression seen in GVS.

Bug 3198736

Change-Id: If12da341c3e13907bdcbb778c8fb4118cd5e3803
Signed-off-by: jwiden <jwiden@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2456791
Reviewed-by: svcguardwords <svcguardwords@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Joshua Widen
2020-12-08 09:54:42 -08:00
committed by Alex Waterman
parent ea5fe7c66c
commit 60f44506a3
7 changed files with 15 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
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@@ -828,7 +828,6 @@ static const struct gops_pmu gm20b_ops_pmu = {
.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
.pmu_mutex_release = gk20a_pmu_mutex_release,
.pmu_is_interrupted = gk20a_pmu_is_interrupted,
.get_irqmask = gk20a_pmu_get_irqmask,
.pmu_isr = gk20a_pmu_isr,
.pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,

1
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
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@@ -910,7 +910,6 @@ static const struct gops_pmu gp10b_ops_pmu = {
.pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
.pmu_mutex_release = gk20a_pmu_mutex_release,
.pmu_is_interrupted = gk20a_pmu_is_interrupted,
.get_irqmask = gk20a_pmu_get_irqmask,
.pmu_isr = gk20a_pmu_isr,
.pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
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@@ -1100,7 +1100,6 @@ static const struct gops_pmu gv11b_ops_pmu = {
.validate_mem_integrity = gv11b_pmu_validate_mem_integrity,
.pmu_enable_irq = gv11b_pmu_enable_irq,
.get_irqdest = gv11b_pmu_get_irqdest,
.get_irqmask = gk20a_pmu_get_irqmask,
.pmu_isr = gk20a_pmu_isr,
.handle_ext_irq = gv11b_pmu_handle_ext_irq,
#ifdef CONFIG_NVGPU_LS_PMU

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
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@@ -1140,7 +1140,6 @@ static const struct gops_pmu tu104_ops_pmu = {
.pmu_get_queue_head = tu104_pmu_queue_head_r,
.pmu_mutex_release = gk20a_pmu_mutex_release,
.pmu_is_interrupted = gk20a_pmu_is_interrupted,
.get_irqmask = gk20a_pmu_get_irqmask,
.pmu_isr = gk20a_pmu_isr,
.pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter,
.pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config,

1
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.h
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@@ -33,7 +33,6 @@ struct pmu_mutexes;
#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEADU
void gk20a_pmu_isr(struct gk20a *g);
u32 gk20a_pmu_get_irqmask(struct gk20a *g);
#ifdef CONFIG_NVGPU_LS_PMU
void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu);

38
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a_fusa.c
View File

@@ -28,40 +28,32 @@
#include "pmu_gk20a.h"
u32 gk20a_pmu_get_irqmask(struct gk20a *g)
{
u32 mask = 0U;
mask = nvgpu_readl(g, pwr_falcon_irqmask_r());
mask &= nvgpu_readl(g, pwr_falcon_irqdest_r());
return mask;
}
void gk20a_pmu_isr(struct gk20a *g)
{
struct nvgpu_pmu *pmu = g->pmu;
u32 intr = 0U;
u32 mask = 0U;
u32 intr, mask;
nvgpu_log_fn(g, " ");
intr = nvgpu_readl(g, pwr_falcon_irqstat_r());
mask = g->ops.pmu.get_irqmask(g);
nvgpu_pmu_dbg(g, "received PMU interrupt: stat:0x%08x mask:0x%08x",
intr, mask);
nvgpu_mutex_acquire(&pmu->isr_mutex);
if (!pmu->isr_enabled || !(intr & mask)) {
nvgpu_log_info(g,
"clearing unhandled interrupt: stat:0x%08x mask:0x%08x",
intr, mask);
nvgpu_writel(g, pwr_falcon_irqsclr_r(), intr);
if (!pmu->isr_enabled) {
nvgpu_mutex_release(&pmu->isr_mutex);
return;
}
intr = intr & mask;
mask = nvgpu_readl(g, pwr_falcon_irqmask_r());
mask &= nvgpu_readl(g, pwr_falcon_irqdest_r());
intr = nvgpu_readl(g, pwr_falcon_irqstat_r());
nvgpu_pmu_dbg(g, "received falcon interrupt: 0x%08x", intr);
intr = nvgpu_readl(g, pwr_falcon_irqstat_r()) & mask;
if (intr == 0U) {
nvgpu_mutex_release(&pmu->isr_mutex);
return;
}
if (g->ops.pmu.handle_ext_irq != NULL) {
g->ops.pmu.handle_ext_irq(g, intr);

1
drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h
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@@ -311,7 +311,6 @@ struct gops_pmu {
void (*pmu_enable_irq)(struct nvgpu_pmu *pmu, bool enable);
u32 (*get_irqdest)(struct gk20a *g);
u32 (*get_irqmask)(struct gk20a *g);
#ifdef CONFIG_NVGPU_LS_PMU
u32 (*get_inst_block_config)(struct gk20a *g);