diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index 0eaa23ab6..40c871ced 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -25,6 +25,9 @@
 #include "gk20a.h"
 #include "hw_ccsr_gk20a.h"
 
+#define NVGPU_TSG_MIN_TIMESLICE_US 1000
+#define NVGPU_TSG_MAX_TIMESLICE_US 50000
+
 static void gk20a_tsg_release(struct kref *ref);
 
 bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch)
@@ -345,6 +348,20 @@ static int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
 	return ret ? ret : g->ops.fifo.update_runlist(g, 0, ~0, true, true);
 }
 
+static int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
+{
+	struct gk20a *g = tsg->g;
+
+	if (timeslice < NVGPU_TSG_MIN_TIMESLICE_US ||
+		timeslice > NVGPU_TSG_MAX_TIMESLICE_US)
+		return -EINVAL;
+
+	gk20a_channel_get_timescale_from_timeslice(g, timeslice,
+			&tsg->timeslice_timeout, &tsg->timeslice_scale);
+
+	return g->ops.fifo.update_runlist(g, 0, ~0, true, true);
+}
+
 static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg)
 {
 	mutex_lock(&f->tsg_inuse_mutex);
@@ -554,6 +571,20 @@ long gk20a_tsg_dev_ioctl(struct file *filp, unsigned int cmd,
 		break;
 		}
 
+	case NVGPU_IOCTL_TSG_SET_TIMESLICE:
+		{
+		err = gk20a_busy(g->dev);
+		if (err) {
+			gk20a_err(dev_from_gk20a(g),
+			   "failed to host gk20a for ioctl cmd: 0x%x", cmd);
+			return err;
+		}
+		err = gk20a_tsg_set_timeslice(tsg,
+			((struct nvgpu_timeslice_args *)buf)->timeslice_us);
+		gk20a_idle(g->dev);
+		break;
+		}
+
 	default:
 		gk20a_err(dev_from_gk20a(g),
 			   "unrecognized tsg gpu ioctl cmd: 0x%x",
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 9f4bf43c1..b8bd21f2f 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -467,11 +467,13 @@ struct nvgpu_gpu_get_gpu_time_args {
 	_IOWR(NVGPU_TSG_IOCTL_MAGIC, 7, struct nvgpu_event_id_ctrl_args)
 #define NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE \
 	_IOW(NVGPU_TSG_IOCTL_MAGIC, 8, struct nvgpu_runlist_interleave_args)
+#define NVGPU_IOCTL_TSG_SET_TIMESLICE \
+	_IOW(NVGPU_TSG_IOCTL_MAGIC, 9, struct nvgpu_timeslice_args)
 
 #define NVGPU_TSG_IOCTL_MAX_ARG_SIZE	\
 	sizeof(struct nvgpu_event_id_ctrl_args)
 #define NVGPU_TSG_IOCTL_LAST		\
-	_IOC_NR(NVGPU_IOCTL_TSG_SET_RUNLIST_INTERLEAVE)
+	_IOC_NR(NVGPU_IOCTL_TSG_SET_TIMESLICE)
 
 
 /*