From 6118009b849e2e307952a5110cf1ef8f75f09b6a Mon Sep 17 00:00:00 2001 From: Jeremy Ho Date: Tue, 2 Jul 2019 16:43:17 +0800 Subject: [PATCH] gpu: nvgpu: remove reversed ordering for deadlock In some cases, we would get deadlock issue due to there are two locks acquisition on common clk driver's lock and nvgpu driver's locks. At the bug, inconsistent lock ordering problem will come with one thread gets "nvgpu lock -> clk lock" and the other thread gets "clk lock -> nvgpu lock". Slove the latter path with one-time initializing clk_parent entry and use cached data afterward. Bug 2555115 Change-Id: I31c5c2728f406307e7cfd4e555f4db0c163234d8 Signed-off-by: Jeremy Ho Reviewed-on: https://git-master.nvidia.com/r/2146727 (cherry picked from commit 42c2bdfb9f1afed4b22f74cb635db52d5f3e7cd0) Reviewed-on: https://git-master.nvidia.com/r/2160290 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/clk/clk_gk20a.h | 1 + drivers/gpu/nvgpu/os/linux/clk.c | 6 +++--- drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c | 11 ++++++++++- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h b/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h index 112285ccd..9cb95715f 100644 --- a/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h +++ b/drivers/gpu/nvgpu/hal/clk/clk_gk20a.h @@ -95,6 +95,7 @@ struct clk_gk20a { struct gk20a *g; #if defined(CONFIG_COMMON_CLK) struct clk *tegra_clk; + struct clk *tegra_clk_parent; struct clk_hw hw; #endif struct pll gpc_pll; diff --git a/drivers/gpu/nvgpu/os/linux/clk.c b/drivers/gpu/nvgpu/os/linux/clk.c index bf8148efb..b9ed903ad 100644 --- a/drivers/gpu/nvgpu/os/linux/clk.c +++ b/drivers/gpu/nvgpu/os/linux/clk.c @@ -91,7 +91,7 @@ static unsigned long nvgpu_linux_get_fmax_at_vmin_safe(struct gk20a *g) */ if (g->clk.tegra_clk) return tegra_dvfs_get_fmax_at_vmin_safe_t( - clk_get_parent(g->clk.tegra_clk)); + g->clk.tegra_clk_parent); if (platform->maxmin_clk_id) return tegra_bpmp_dvfs_get_fmax_at_vmin( @@ -117,7 +117,7 @@ static int nvgpu_linux_predict_mv_at_hz_cur_tfloor(struct clk_gk20a *clk, unsigned long rate) { return tegra_dvfs_predict_mv_at_hz_cur_tfloor( - clk_get_parent(clk->tegra_clk), rate); + clk->tegra_clk_parent, rate); } static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain) @@ -126,7 +126,7 @@ static unsigned long nvgpu_linux_get_maxrate(struct gk20a *g, u32 api_domain) switch (api_domain) { case CTRL_CLK_DOMAIN_GPCCLK: - ret = tegra_dvfs_get_maxrate(clk_get_parent(g->clk.tegra_clk)); + ret = tegra_dvfs_get_maxrate(g->clk.tegra_clk_parent); break; default: nvgpu_err(g, "unknown clock: %u", api_domain); diff --git a/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c index 6be3d4d79..9ee8619ed 100644 --- a/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/os/linux/platform_gk20a_tegra.c @@ -649,7 +649,7 @@ int gk20a_tegra_init_secure_alloc(struct gk20a_platform *platform) static struct clk *gk20a_clk_get(struct gk20a *g) { if (!g->clk.tegra_clk) { - struct clk *clk; + struct clk *clk, *clk_parent; char clk_dev_id[32]; struct device *dev = dev_from_gk20a(g); @@ -661,7 +661,16 @@ static struct clk *gk20a_clk_get(struct gk20a *g) clk_dev_id); return NULL; } + + clk_parent = clk_get_parent(clk); + if (IS_ERR_OR_NULL(clk_parent)) { + nvgpu_err(g, "fail to get tegra gpu clk parent%s/gpu\n", + clk_dev_id); + return NULL; + } + g->clk.tegra_clk = clk; + g->clk.tegra_clk_parent = clk_parent; } return g->clk.tegra_clk;