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gpu: nvgpu: print intr code for class error

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Print interrupt code and channel id for unhandled gr class error.

Bug 200010403

Change-Id: Iedceaf4b8b6363b26f1836256875fb9b5c43eded
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/419566
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2014-06-05 18:07:57 +05:30
committed by Dan Willemsen
parent 3f8d5536a0
commit 614b804159
1 changed files with 5 additions and 2 deletions
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7
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -4898,13 +4898,16 @@ static int gk20a_gr_handle_class_error(struct gk20a *g,
{ {
struct fifo_gk20a *f = &g->fifo; struct fifo_gk20a *f = &g->fifo;
struct channel_gk20a *ch = &f->channel[isr_data->chid]; struct channel_gk20a *ch = &f->channel[isr_data->chid];
u32 gr_class_error =
gr_class_error_code_v(gk20a_readl(g, gr_class_error_r()));
gk20a_dbg_fn(""); gk20a_dbg_fn("");
gk20a_set_error_notifier(ch, gk20a_set_error_notifier(ch,
NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY); NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY);
gk20a_err(dev_from_gk20a(g), gk20a_err(dev_from_gk20a(g),
"class error 0x%08x, offset 0x%08x", "class error 0x%08x, offset 0x%08x, unhandled intr 0x%08x for channel %u\n",
isr_data->class_num, isr_data->offset); isr_data->class_num, isr_data->offset,
gr_class_error, ch->hw_chid);
return -EINVAL; return -EINVAL;
} }