From 6196d3f382d1cab64d609ce74bc15a94bd1b2c91 Mon Sep 17 00:00:00 2001 From: Austin Tajiri Date: Tue, 7 Mar 2023 02:50:36 +0000 Subject: [PATCH] gpu: nvgpu: ga10b: fix missing gr registers Add the following missing GR registers/fields for GA10B: - gr_exception_fe_m - gr_exception_memfmt_m - gr_exception_pd_m - gr_exception_scc_m - gr_exception_ds_m - gr_exception_ssync_m - gr_exception_mme_m - gr_exception_sked_m - gr_fe_hww_esr_info_r - gr_mme_hww_esr_info_r - gr_sked_hww_esr_r - gr_sked_hww_esr_reset_active_f Jira NVGPU-9217 Change-Id: I7bffb0f4e605ee09e75c7f550cece6779b71a80e Signed-off-by: Austin Tajiri Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2866781 Reviewed-by: svcacv Reviewed-by: Tejal Kudav Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit --- .../gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h index 1f899626d..3e2440822 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_gr_ga10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -92,6 +92,14 @@ #define gr_intr_retrigger_r() (0x00400158U) #define gr_intr_retrigger_trigger_true_f() (0x1U) #define gr_exception_r() (0x00400108U) +#define gr_exception_fe_m() (U32(0x1U) << 0U) +#define gr_exception_memfmt_m() (U32(0x1U) << 1U) +#define gr_exception_pd_m() (U32(0x1U) << 2U) +#define gr_exception_scc_m() (U32(0x1U) << 3U) +#define gr_exception_ds_m() (U32(0x1U) << 4U) +#define gr_exception_ssync_m() (U32(0x1U) << 5U) +#define gr_exception_mme_m() (U32(0x1U) << 7U) +#define gr_exception_sked_m() (U32(0x1U) << 8U) #define gr_exception_gpc_m() (U32(0x1U) << 24U) #define gr_exception_mme_fe1_m() (U32(0x1U) << 9U) #define gr_exception1_r() (0x00400118U) @@ -406,6 +414,7 @@ #define gr_fe_hww_esr_r() (0x00404000U) #define gr_fe_hww_esr_reset_active_f() (0x40000000U) #define gr_fe_hww_esr_en_enable_f() (0x80000000U) +#define gr_fe_hww_esr_info_r() (0x004041b0U) #define gr_mme_fe1_hww_esr_r() (0x0040a790U) #define gr_mme_fe1_hww_esr_reset_active_f() (0x40000000U) #define gr_mme_fe1_hww_esr_en_enable_f() (0x80000000U) @@ -454,6 +463,7 @@ #define gr_mme_hww_esr_r() (0x00404490U) #define gr_mme_hww_esr_reset_active_f() (0x40000000U) #define gr_mme_hww_esr_en_enable_f() (0x80000000U) +#define gr_mme_hww_esr_info_r() (0x00404494U) #define gr_memfmt_hww_esr_r() (0x00404600U) #define gr_memfmt_hww_esr_reset_active_f() (0x40000000U) #define gr_memfmt_hww_esr_en_enable_f() (0x80000000U) @@ -658,6 +668,8 @@ #define gr_scc_hww_esr_r() (0x00408030U) #define gr_scc_hww_esr_reset_active_f() (0x40000000U) #define gr_scc_hww_esr_en_enable_f() (0x80000000U) +#define gr_sked_hww_esr_r() (0x00407020U) +#define gr_sked_hww_esr_reset_active_f() (0x40000000U) #define gr_ssync_hww_esr_r() (0x00405a14U) #define gr_ssync_hww_esr_reset_active_f() (0x40000000U) #define gr_ssync_hww_esr_en_enable_f() (0x80000000U)