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gpu: nvgpu: split sema sync hal to wait and incr

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Instead of one HAL op with a boolean flag to decide whether to do one
thing or another entirely different thing, use two separate HAL ops for
filling priv cmd bufs with semaphore wait and semaphore increment
commands. It's already two ops for syncpoints, and explicit commands are
more readable than boolean flags.

Change offset into cmdbuf in sem wait HAL to be relative to the cmdbuf,
so the HAL adds the cmdbuf internal offset to it.

While at it, modify the syncpoint cmdbuf HAL ops' prototypes to be
consistent.

Jira NVGPU-4548

Change-Id: Ibac1fc5fe2ef113e4e16b56358ecfa8904464c82
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323319
(cherry picked from commit 08c1fa38c0fe4effe6ff7a992af55f46e03e77d0)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328409
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Hölttä
2020-04-03 14:04:02 +03:00
committed by Alex Waterman
parent 6a7bf6cdc0
commit 6202ead057
17 changed files with 149 additions and 96 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/hal/sync/syncpt_cmdbuf_gk20a.h
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@@ -33,12 +33,12 @@ struct nvgpu_mem;
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va);
u32 id, u32 thresh, u64 gpu_va_base);
u32 gk20a_syncpt_get_wait_cmd_size(void);
u32 gk20a_syncpt_get_incr_per_release(void);
void gk20a_syncpt_add_incr_cmd(struct gk20a *g,
bool wfi_cmd, struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va);
struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va, bool wfi);
u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd);
#endif
@@ -53,7 +53,7 @@ int gk20a_syncpt_alloc_buf(struct nvgpu_channel *c,
#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
static inline void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
struct priv_cmd_entry *cmd, u32 off,
u32 id, u32 thresh, u64 gpu_va)
u32 id, u32 thresh, u64 gpu_va_base)
{
}
static inline u32 gk20a_syncpt_get_wait_cmd_size(void)
@@ -65,8 +65,8 @@ static inline u32 gk20a_syncpt_get_incr_per_release(void)
return 0U;
}
static inline void gk20a_syncpt_add_incr_cmd(struct gk20a *g,
bool wfi_cmd, struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va)
struct priv_cmd_entry *cmd,
u32 id, u64 gpu_va, bool wfi)
{
}
static inline u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd)
@@ -87,4 +87,4 @@ static inline int gk20a_syncpt_alloc_buf(struct nvgpu_channel *c,
#endif
#endif /* NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H */
#endif /* NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H */