diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c
index dd27953ef..2822282db 100644
--- a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c
+++ b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -52,17 +52,16 @@ void gk20a_fifo_intr_1_enable(struct gk20a *g, bool enable)
 u32 gk20a_fifo_intr_1_isr(struct gk20a *g)
 {
 	u32 fifo_intr = nvgpu_readl(g, fifo_intr_0_r());
-	u32 clear_intr = 0U;
 
-	nvgpu_log(g, gpu_dbg_intr, "fifo nonstall isr %08x\n", fifo_intr);
+	nvgpu_log(g, gpu_dbg_intr, "fifo nonstall isr 0x%08x", fifo_intr);
 
 	if ((fifo_intr & fifo_intr_0_channel_intr_pending_f()) != 0U) {
-		clear_intr = fifo_intr_0_channel_intr_pending_f();
+		nvgpu_writel(g, fifo_intr_0_r(),
+			fifo_intr_0_channel_intr_pending_f());
+		return NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE;
 	}
 
-	nvgpu_writel(g, fifo_intr_0_r(), clear_intr);
-
-	return NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE;
+	return 0U;
 }
 
 void gk20a_fifo_intr_handle_chsw_error(struct gk20a *g)
diff --git a/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c b/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c
index 4b487c388..0d2a1d1ac 100644
--- a/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c
+++ b/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -92,7 +92,8 @@ int test_gk20a_fifo_intr_1_isr(struct unit_module *m,
 	/* no channel intr pending */
 	nvgpu_writel(g, fifo_intr_0_r(), ~fifo_intr_0_channel_intr_pending_f());
 	gk20a_fifo_intr_1_isr(g);
-	unit_assert(nvgpu_readl(g, fifo_intr_0_r()) == 0, goto done);
+	unit_assert(nvgpu_readl(g, fifo_intr_0_r()) ==
+		~fifo_intr_0_channel_intr_pending_f(), goto done);
 
 	/* channel intr pending */
 	nvgpu_writel(g, fifo_intr_0_r(), U32_MAX);