From 625d942c522f10f87a933c000aaee230f016ddc1 Mon Sep 17 00:00:00 2001 From: Vedashree Vidwans Date: Tue, 2 Feb 2021 14:23:11 -0800 Subject: [PATCH] gpu: nvgpu: update gops_fifo.intr_1_isr logic Update gops_fifo.intr_1_isr to clear interrupt and return NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE only if channel interrupt is pending Jira NVGPU-6222 Change-Id: I976f8bcf53c7735b154f40bb70b5f401020c8dd4 Signed-off-by: Vedashree Vidwans Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2479250 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svc-mobile-cert Reviewed-by: Seema Khowala Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c | 13 ++++++------- .../units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c | 5 +++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c index dd27953ef..2822282db 100644 --- a/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c +++ b/drivers/gpu/nvgpu/hal/fifo/fifo_intr_gk20a_fusa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -52,17 +52,16 @@ void gk20a_fifo_intr_1_enable(struct gk20a *g, bool enable) u32 gk20a_fifo_intr_1_isr(struct gk20a *g) { u32 fifo_intr = nvgpu_readl(g, fifo_intr_0_r()); - u32 clear_intr = 0U; - nvgpu_log(g, gpu_dbg_intr, "fifo nonstall isr %08x\n", fifo_intr); + nvgpu_log(g, gpu_dbg_intr, "fifo nonstall isr 0x%08x", fifo_intr); if ((fifo_intr & fifo_intr_0_channel_intr_pending_f()) != 0U) { - clear_intr = fifo_intr_0_channel_intr_pending_f(); + nvgpu_writel(g, fifo_intr_0_r(), + fifo_intr_0_channel_intr_pending_f()); + return NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE; } - nvgpu_writel(g, fifo_intr_0_r(), clear_intr); - - return NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE; + return 0U; } void gk20a_fifo_intr_handle_chsw_error(struct gk20a *g) diff --git a/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c b/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c index 4b487c388..0d2a1d1ac 100644 --- a/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c +++ b/userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -92,7 +92,8 @@ int test_gk20a_fifo_intr_1_isr(struct unit_module *m, /* no channel intr pending */ nvgpu_writel(g, fifo_intr_0_r(), ~fifo_intr_0_channel_intr_pending_f()); gk20a_fifo_intr_1_isr(g); - unit_assert(nvgpu_readl(g, fifo_intr_0_r()) == 0, goto done); + unit_assert(nvgpu_readl(g, fifo_intr_0_r()) == + ~fifo_intr_0_channel_intr_pending_f(), goto done); /* channel intr pending */ nvgpu_writel(g, fifo_intr_0_r(), U32_MAX);