From 62b04331deae7cfc494581567772e26a5434c739 Mon Sep 17 00:00:00 2001 From: Sagar Kamble Date: Mon, 23 Aug 2021 14:06:49 +0530 Subject: [PATCH] gpu: nvgpu: compile out priv_access_map config/addr hals These hals are non-safe. Compile them out with CONFIG_NVGPU_SET_FALCON_ACCESS_MAP. JIRA NVGPU-5358 Change-Id: I75b46e201fa132e09fee15679a402d24bbf9b2ab Signed-off-by: Sagar Kamble Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2581360 (cherry picked from commit d048333ef391019b2618abf7d09c8fe2042f8ee0) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2581841 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/gr/ctx.c | 2 ++ drivers/gpu/nvgpu/common/gr/subctx.c | 2 ++ .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c | 25 +++++++++++++++++++ .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h | 2 ++ .../hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c | 25 ------------------- drivers/gpu/nvgpu/hal/init/hal_ga100.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_ga10b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gm20b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gp10b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_gv11b.c | 2 ++ drivers/gpu/nvgpu/hal/init/hal_tu104.c | 2 ++ .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c | 2 ++ .../gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c | 2 ++ drivers/gpu/nvgpu/include/nvgpu/gops/gr.h | 2 ++ userspace/units/gr/setup/nvgpu-gr-setup.h | 2 -- 15 files changed, 49 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/nvgpu/common/gr/ctx.c b/drivers/gpu/nvgpu/common/gr/ctx.c index f2897a1a6..1aadf9671 100644 --- a/drivers/gpu/nvgpu/common/gr/ctx.c +++ b/drivers/gpu/nvgpu/common/gr/ctx.c @@ -497,12 +497,14 @@ void nvgpu_gr_ctx_load_golden_ctx_image(struct gk20a *g, } #endif +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP /* set priv access map */ g->ops.gr.ctxsw_prog.set_priv_access_map_config_mode(g, mem, g->allow_all); g->ops.gr.ctxsw_prog.set_priv_access_map_addr(g, mem, nvgpu_gr_ctx_get_global_ctx_va(gr_ctx, NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA)); +#endif /* disable verif features */ g->ops.gr.ctxsw_prog.disable_verif_features(g, mem); diff --git a/drivers/gpu/nvgpu/common/gr/subctx.c b/drivers/gpu/nvgpu/common/gr/subctx.c index 6330285d1..1334b7d57 100644 --- a/drivers/gpu/nvgpu/common/gr/subctx.c +++ b/drivers/gpu/nvgpu/common/gr/subctx.c @@ -93,10 +93,12 @@ void nvgpu_gr_subctx_load_ctx_header(struct gk20a *g, nvgpu_err(g, "l2_flush failed"); } +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP /* set priv access map */ g->ops.gr.ctxsw_prog.set_priv_access_map_addr(g, ctxheader, nvgpu_gr_ctx_get_global_ctx_va(gr_ctx, NVGPU_GR_CTX_PRIV_ACCESS_MAP_VA)); +#endif g->ops.gr.ctxsw_prog.set_patch_addr(g, ctxheader, nvgpu_gr_ctx_get_patch_ctx_mem(gr_ctx)->gpu_va); diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c index a7c7151de..836d65f23 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c @@ -37,6 +37,31 @@ void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g, ctxsw_prog_main_image_preemption_options_control_cta_enabled_f()); } +void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g, + struct nvgpu_mem *ctx_mem, bool allow_all) +{ + if (allow_all) { + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_config_o(), + ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f()); + } else { + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_config_o(), + ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f()); + } +} + +void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g, + struct nvgpu_mem *ctx_mem, u64 addr) +{ + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_addr_lo_o(), + u64_lo32(addr)); + nvgpu_mem_wr(g, ctx_mem, + ctxsw_prog_main_image_priv_access_map_addr_hi_o(), + u64_hi32(addr)); +} + #ifdef CONFIG_NVGPU_FECS_TRACE u32 gm20b_ctxsw_prog_hw_get_ts_tag_invalid_timestamp(void) { diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h index dc55f15af..164a606c4 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h @@ -36,10 +36,12 @@ void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#if defined(CONFIG_NVGPU_SET_FALCON_ACCESS_MAP) void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool allow_all); void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); +#endif void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, struct nvgpu_mem *ctx_mem); #if defined(CONFIG_NVGPU_HAL_NON_FUSA) diff --git a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c index e89acf2c5..3ba6d5ba5 100644 --- a/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c @@ -63,31 +63,6 @@ void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g, ctxsw_prog_main_image_num_restore_ops_o(), 0); } -void gm20b_ctxsw_prog_set_config_mode_priv_access_map(struct gk20a *g, - struct nvgpu_mem *ctx_mem, bool allow_all) -{ - if (allow_all) { - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_config_o(), - ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f()); - } else { - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_config_o(), - ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f()); - } -} - -void gm20b_ctxsw_prog_set_addr_priv_access_map(struct gk20a *g, - struct nvgpu_mem *ctx_mem, u64 addr) -{ - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_addr_lo_o(), - u64_lo32(addr)); - nvgpu_mem_wr(g, ctx_mem, - ctxsw_prog_main_image_priv_access_map_addr_hi_o(), - u64_hi32(addr)); -} - void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g, struct nvgpu_mem *ctx_mem) { diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga100.c b/drivers/gpu/nvgpu/hal/init/hal_ga100.c index b481e43df..7baaf9ba5 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga100.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga100.c @@ -446,8 +446,10 @@ static const struct gops_gr_ctxsw_prog ga100_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, diff --git a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c index b01bef164..455db457b 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_ga10b.c @@ -410,8 +410,10 @@ static const struct gops_gr_ctxsw_prog ga10b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c index b1d01436f..3cd6de639 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c @@ -201,8 +201,10 @@ static const struct gops_gr_ctxsw_prog gm20b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gm20b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gm20b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c index 9d77f58bb..b2685614f 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c @@ -256,8 +256,10 @@ static const struct gops_gr_ctxsw_prog gp10b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gm20b_ctxsw_prog_set_zcull_ptr, diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c index a2c62627b..53a5c6ab3 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c @@ -333,8 +333,10 @@ static const struct gops_gr_ctxsw_prog gv11b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c index c515b1ae3..b37f1a326 100644 --- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c +++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c @@ -377,8 +377,10 @@ static const struct gops_gr_ctxsw_prog tu104_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, .set_context_buffer_ptr = gv11b_ctxsw_prog_set_context_buffer_ptr, .set_type_per_veid_header = gv11b_ctxsw_prog_set_type_per_veid_header, diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c index 33df3d5d1..ff2d85228 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c @@ -280,8 +280,10 @@ static const struct gops_gr_ctxsw_prog vgpu_ga10b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, diff --git a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c index 53fe528f3..b3dc195a7 100644 --- a/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c @@ -251,8 +251,10 @@ static const struct gops_gr_ctxsw_prog vgpu_gv11b_ops_gr_ctxsw_prog = { .set_patch_addr = gm20b_ctxsw_prog_set_patch_addr, .init_ctxsw_hdr_data = gp10b_ctxsw_prog_init_ctxsw_hdr_data, .set_compute_preemption_mode_cta = gp10b_ctxsw_prog_set_compute_preemption_mode_cta, +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP .set_priv_access_map_config_mode = gm20b_ctxsw_prog_set_config_mode_priv_access_map, .set_priv_access_map_addr = gm20b_ctxsw_prog_set_addr_priv_access_map, +#endif .disable_verif_features = gm20b_ctxsw_prog_disable_verif_features, #ifdef CONFIG_NVGPU_GRAPHICS .set_zcull_ptr = gv11b_ctxsw_prog_set_zcull_ptr, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h index af5ea5244..3900d70a2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gops/gr.h @@ -908,11 +908,13 @@ struct gops_gr_ctxsw_prog { u64 addr); void (*set_type_per_veid_header)(struct gk20a *g, struct nvgpu_mem *ctx_mem); +#ifdef CONFIG_NVGPU_SET_FALCON_ACCESS_MAP void (*set_priv_access_map_config_mode)(struct gk20a *g, struct nvgpu_mem *ctx_mem, bool allow_all); void (*set_priv_access_map_addr)(struct gk20a *g, struct nvgpu_mem *ctx_mem, u64 addr); +#endif void (*disable_verif_features)(struct gk20a *g, struct nvgpu_mem *ctx_mem); void (*init_ctxsw_hdr_data)(struct gk20a *g, diff --git a/userspace/units/gr/setup/nvgpu-gr-setup.h b/userspace/units/gr/setup/nvgpu-gr-setup.h index 1b8da685f..58e7ac7bc 100644 --- a/userspace/units/gr/setup/nvgpu-gr-setup.h +++ b/userspace/units/gr/setup/nvgpu-gr-setup.h @@ -58,8 +58,6 @@ struct unit_module; * nvgpu_gr_ctx_get_global_ctx_va, * gops_gr_setup.alloc_obj_ctx, * nvgpu_gr_ctx_load_golden_ctx_image, - * gm20b_ctxsw_prog_set_config_mode_priv_access_map, - * gm20b_ctxsw_prog_set_addr_priv_access_map, * gm20b_ctxsw_prog_set_patch_addr, * gm20b_ctxsw_prog_disable_verif_features, * gv11b_gr_init_commit_global_attrib_cb,