mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 10:34:43 +03:00
gpu: nvgpu: update the config options & makefile
Added dependency between the Kconfig options as follows where '->' indicates 'depends on' relation: SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA DGPU -> GK20A_PCI Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI as well. DGPU related sources are now compiled under config flag DGPU. Also update conditional compilation of the driver paths w.r.t DGPU, VPR and COMPRESSION flags. Bug 2834141 Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Alex Waterman
parent
ef69bbc92b
commit
630eaa46cb
@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017-2019 NVIDIA Corporation. All rights reserved.
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* Copyright (C) 2017-2020 NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@@ -430,10 +430,12 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
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nvgpu_kmem_debugfs_init(g);
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#endif
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nvgpu_ltc_debugfs_init(g);
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#ifdef CONFIG_NVGPU_DGPU
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if (g->pci_vendor_id) {
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nvgpu_xve_debugfs_init(g);
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nvgpu_bios_debugfs_init(g);
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}
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#endif
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}
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void gk20a_debug_deinit(struct gk20a *g)
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@@ -34,6 +34,7 @@
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enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g,
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struct dma_buf *dmabuf)
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{
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#ifdef CONFIG_NVGPU_DGPU
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struct gk20a *buf_owner = nvgpu_vidmem_buf_owner(dmabuf);
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bool unified_memory = nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY);
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@@ -49,12 +50,12 @@ enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g,
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} else if (buf_owner != g) {
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/* Someone else's vidmem */
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return APERTURE_INVALID;
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}
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#ifdef CONFIG_NVGPU_DGPU
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else {
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} else {
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/* Yay, buf_owner == g */
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return APERTURE_VIDMEM;
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}
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#else
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return APERTURE_SYSMEM;
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#endif
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}
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@@ -322,7 +322,13 @@ gk20a_ctrl_ioctl_gpu_characteristics(
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gpu.bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */
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#ifdef CONFIG_NVGPU_COMPRESSION
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gpu.compression_page_size = g->ops.fb.compression_page_size(g);
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gpu.gr_compbit_store_base_hw = g->cbc->compbit_store.base_hw;
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gpu.gr_gobs_per_comptagline_per_slice =
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g->cbc->gobs_per_comptagline_per_slice;
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gpu.cbc_comptags_per_line = g->cbc->comptags_per_cacheline;
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#endif
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gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g);
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@@ -377,20 +383,18 @@ gk20a_ctrl_ioctl_gpu_characteristics(
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gpu.fbp_en_mask = nvgpu_fbp_get_fbp_en_mask(g->fbp);;
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gpu.max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g);
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gpu.max_lts_per_ltc = g->ops.top.get_max_lts_per_ltc(g);
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gpu.gr_compbit_store_base_hw = g->cbc->compbit_store.base_hw;
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gpu.gr_gobs_per_comptagline_per_slice =
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g->cbc->gobs_per_comptagline_per_slice;
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gpu.num_ltc = nvgpu_ltc_get_ltc_count(g);
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gpu.lts_per_ltc = nvgpu_ltc_get_slices_per_ltc(g);
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gpu.cbc_cache_line_size = nvgpu_ltc_get_cacheline_size(g);
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gpu.cbc_comptags_per_line = g->cbc->comptags_per_cacheline;
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if ((g->ops.clk.get_maxrate) && nvgpu_platform_is_silicon(g)) {
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gpu.max_freq = g->ops.clk.get_maxrate(g,
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CTRL_CLK_DOMAIN_GPCCLK);
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}
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#ifdef CONFIG_NVGPU_DGPU
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gpu.local_video_memory_size = g->mm.vidmem.size;
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#endif
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gpu.pci_vendor_id = g->pci_vendor_id;
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gpu.pci_device_id = g->pci_device_id;
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@@ -995,6 +999,7 @@ clean_up:
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return err;
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}
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#ifdef CONFIG_NVGPU_DGPU
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static int nvgpu_gpu_alloc_vidmem(struct gk20a *g,
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struct nvgpu_gpu_alloc_vidmem_args *args)
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{
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@@ -1059,6 +1064,7 @@ static int nvgpu_gpu_get_memory_state(struct gk20a *g,
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return err;
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}
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#endif
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static u32 nvgpu_gpu_convert_clk_domain(u32 clk_domain)
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{
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@@ -1936,6 +1942,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
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(struct nvgpu_gpu_get_engine_info_args *)buf);
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break;
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#ifdef CONFIG_NVGPU_DGPU
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case NVGPU_GPU_IOCTL_ALLOC_VIDMEM:
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err = nvgpu_gpu_alloc_vidmem(g,
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(struct nvgpu_gpu_alloc_vidmem_args *)buf);
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@@ -1945,6 +1952,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
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err = nvgpu_gpu_get_memory_state(g,
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(struct nvgpu_gpu_get_memory_state_args *)buf);
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break;
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#endif
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case NVGPU_GPU_IOCTL_CLK_GET_RANGE:
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err = nvgpu_gpu_clk_get_range(g, priv,
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@@ -1,7 +1,7 @@
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/*
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* Tegra GK20A GPU Debugger/Profiler Driver
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*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -1565,6 +1565,7 @@ nvgpu_dbg_gpu_ioctl_suspend_resume_contexts(struct dbg_session_gk20a *dbg_s,
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return err;
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}
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#ifdef CONFIG_NVGPU_DGPU
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static int nvgpu_dbg_gpu_ioctl_access_fb_memory(struct dbg_session_gk20a *dbg_s,
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struct nvgpu_dbg_gpu_access_fb_memory_args *args)
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{
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@@ -1643,6 +1644,7 @@ fail_dmabuf_put:
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return err;
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}
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#endif
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static int nvgpu_ioctl_profiler_reserve(struct dbg_session_gk20a *dbg_s,
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struct nvgpu_dbg_gpu_profiler_reserve_args *args)
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@@ -2123,10 +2125,12 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
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(struct nvgpu_dbg_gpu_suspend_resume_contexts_args *)buf);
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break;
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#ifdef CONFIG_NVGPU_DGPU
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case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY:
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err = nvgpu_dbg_gpu_ioctl_access_fb_memory(dbg_s,
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(struct nvgpu_dbg_gpu_access_fb_memory_args *)buf);
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break;
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#endif
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case NVGPU_DBG_GPU_IOCTL_PROFILER_ALLOCATE:
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err = nvgpu_ioctl_allocate_profiler_object(dbg_s_linux,
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@@ -25,6 +25,7 @@
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#include <nvgpu/vidmem.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/string.h>
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#include <nvgpu/nvgpu_sgt.h>
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#include <nvgpu/nvgpu_sgt_os.h>
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#include <nvgpu/linux/dma.h>
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@@ -106,6 +107,7 @@ static u64 nvgpu_mem_get_addr_sysmem(struct gk20a *g, struct nvgpu_mem *mem)
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*/
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u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem)
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{
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#ifdef CONFIG_NVGPU_DGPU
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struct nvgpu_page_alloc *alloc;
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if (mem->aperture == APERTURE_SYSMEM)
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@@ -120,6 +122,12 @@ u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem)
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WARN_ON(alloc->nr_chunks != 1);
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return alloc->base;
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#else
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if (mem->aperture == APERTURE_SYSMEM)
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return nvgpu_mem_get_addr_sysmem(g, mem);
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return 0;
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#endif
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}
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/*
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@@ -274,6 +282,7 @@ static const struct nvgpu_sgt_ops nvgpu_linux_sgt_ops = {
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.sgt_free = nvgpu_mem_linux_sgl_free,
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};
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#ifdef CONFIG_NVGPU_DGPU
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static struct nvgpu_sgt *__nvgpu_mem_get_sgl_from_vidmem(
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struct gk20a *g,
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struct scatterlist *linux_sgl)
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@@ -286,14 +295,17 @@ static struct nvgpu_sgt *__nvgpu_mem_get_sgl_from_vidmem(
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return &vidmem_alloc->sgt;
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}
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#endif
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struct nvgpu_sgt *nvgpu_linux_sgt_create(struct gk20a *g, struct sg_table *sgt)
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{
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struct nvgpu_sgt *nvgpu_sgt;
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struct scatterlist *linux_sgl = sgt->sgl;
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#ifdef CONFIG_NVGPU_DGPU
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if (nvgpu_addr_is_vidmem_page_alloc(sg_dma_address(linux_sgl)))
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return __nvgpu_mem_get_sgl_from_vidmem(g, linux_sgl);
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#endif
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nvgpu_sgt = nvgpu_kzalloc(g, sizeof(*nvgpu_sgt));
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if (!nvgpu_sgt)
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -35,15 +35,17 @@ int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
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case NVGPU_GPUID_GP10B:
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nvgpu_gp10b_init_os_ops(l);
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break;
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case NVGPU_GPUID_GV100:
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nvgpu_gv100_init_os_ops(l);
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break;
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case NVGPU_GPUID_GV11B:
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nvgpu_gv11b_init_os_ops(l);
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break;
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#ifdef CONFIG_NVGPU_DGPU
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case NVGPU_GPUID_GV100:
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nvgpu_gv100_init_os_ops(l);
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break;
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case NVGPU_GPUID_TU104:
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nvgpu_tu104_init_os_ops(l);
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break;
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#endif
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default:
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break;
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}
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@@ -23,6 +23,7 @@
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#include <nvgpu/rbtree.h>
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#include <nvgpu/vm_area.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/nvgpu_sgt.h>
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#include <nvgpu/page_allocator.h>
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#include <nvgpu/vidmem.h>
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#include <nvgpu/utils.h>
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