gpu: nvgpu: update the config options & makefile

Added dependency between the Kconfig options as follows where
'->' indicates 'depends on' relation:

SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA
DGPU -> GK20A_PCI

Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI
as well. DGPU related sources are now compiled under config flag DGPU.
Also update conditional compilation of the driver paths w.r.t DGPU,
VPR and COMPRESSION flags.

Bug 2834141

Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Kconfig

@@ -120,13 +120,6 @@ config GK20A_TRACE_PRINTK
 	  Enable nvgpu debug facility to redirect debug spew to ftrace. This
 	  affects kernel memory use, so should not be enabled by default.
 
-config NVGPU_SUPPORT_CDE
-	bool "Support extraction of comptags for CDE"
-	depends on GK20A
-	default y
-	help
-	  Enable support for extraction of comptags for CDE.
-
 config NVGPU_USE_TEGRA_ALLOC_FD
 	bool "Use tegra_alloc_fd() for allocating dma_buf fds for vidmem"
 	depends on GK20A
@@ -159,13 +152,6 @@ config NVGPU_LS_PMU
 	help
 	  Support for iGPU LS PMU enable/disable
 
-config NVGPU_COMPRESSION
-	bool "Compression support"
-	depends on GK20A
-	default y
-	help
-	  Support for compression
-
 config NVGPU_LOGGING
 	bool "NVGPU logging"
 	depends on GK20A
@@ -208,3 +194,34 @@ config NVGPU_DMABUF_HAS_DRVDATA
 	default y
 	help
 	  Support NVGPU DMABUF private driver data needed for compression
+
+config NVGPU_COMPRESSION
+	bool "Compression support"
+	depends on GK20A
+	depends on NVGPU_DMABUF_HAS_DRVDATA
+	default y
+	help
+	  Support for compression
+
+config NVGPU_SUPPORT_CDE
+	bool "Support extraction of comptags for CDE"
+	depends on GK20A
+	depends on NVGPU_COMPRESSION
+	default y
+	help
+	  Enable support for extraction of comptags for CDE.
+
+config NVGPU_DGPU
+	bool "NVGPU DGPU support"
+	depends on GK20A
+	depends on GK20A_PCI
+	default y
+	help
+	  Support for NVGPU DGPU
+
+config NVGPU_VPR
+	bool "NVGPU VPR support"
+	depends on GK20A
+	default y
+	help
+	  Support for NVGPU VPR

drivers/gpu/nvgpu/Makefile

@@ -29,8 +29,6 @@ ccflags-y += -DCONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
 ccflags-y += -DCONFIG_NVGPU_USERD
 ccflags-y += -DCONFIG_NVGPU_CHANNEL_WDT
 ccflags-y += -DCONFIG_NVGPU_LS_PMU
-ccflags-y += -DCONFIG_NVGPU_DGPU
-ccflags-y += -DCONFIG_NVGPU_VPR
 ccflags-y += -DCONFIG_NVGPU_CILP
 ccflags-y += -DCONFIG_NVGPU_REPLAYABLE_FAULT
 ccflags-y += -DCONFIG_NVGPU_GRAPHICS
@@ -38,7 +36,6 @@ ccflags-y += -DCONFIG_NVGPU_CHANNEL_TSG_SCHEDULING
 ccflags-y += -DCONFIG_NVGPU_CHANNEL_TSG_CONTROL
 ccflags-y += -DCONFIG_NVGPU_POWER_PG
 ccflags-y += -DCONFIG_NVGPU_KERNEL_MODE_SUBMIT
-ccflags-y += -DCONFIG_NVGPU_COMPRESSION
 ccflags-y += -DCONFIG_NVGPU_SIM
 ccflags-y += -DCONFIG_NVGPU_TRACE
 ccflags-y += -DCONFIG_NVGPU_SYSFS
@@ -74,6 +71,108 @@ obj-$(CONFIG_GK20A) := nvgpu.o
 # OS independent parts of nvgpu. The work to collect files here
 # is in progress.
 
+ifeq ($(CONFIG_NVGPU_DGPU),y)
+nvgpu-$(CONFIG_NVGPU_DGPU) += \
+	os/linux/dmabuf_vidmem.o \
+	os/linux/os_ops_gv100.o \
+	os/linux/os_ops_tu104.o \
+	common/sec2/sec2.o \
+	common/sec2/sec2_allocator.o \
+	common/sec2/sec2_lsfm.o \
+	common/sec2/ipc/sec2_cmd.o \
+	common/sec2/ipc/sec2_msg.o \
+	common/sec2/ipc/sec2_queue.o \
+	common/sec2/ipc/sec2_seq.o \
+	common/vbios/bios_sw_gv100.o \
+	common/vbios/bios_sw_tu104.o \
+	common/falcon/falcon_sw_tu104.o \
+	common/acr/acr_sw_tu104.o \
+	common/mm/allocators/page_allocator.o \
+	common/mm/vidmem.o \
+	common/pramin.o \
+	common/ce/ce_app.o \
+	common/clk_arb/clk_arb_gv100.o \
+	common/engine_queues/engine_emem_queue.o \
+	hal/mm/mm_gv100.o \
+	hal/mm/mm_tu104.o \
+	hal/mc/mc_gv100.o  \
+	hal/mc/mc_tu104.o  \
+	hal/bus/bus_gv100.o \
+	hal/bus/bus_tu104.o \
+	hal/class/class_tu104.o \
+	hal/clk/clk_tu104.o \
+	hal/gr/init/gr_init_gv100.o \
+	hal/gr/init/gr_init_tu104.o \
+	hal/gr/intr/gr_intr_tu104.o \
+	hal/fbpa/fbpa_tu104.o \
+	hal/init/hal_tu104.o \
+	hal/init/hal_tu104_litter.o \
+	hal/power_features/cg/tu104_gating_reglist.o \
+	hal/ltc/ltc_tu104.o \
+	hal/fb/fb_gv100.o \
+	hal/fb/fb_tu104.o \
+	hal/fb/fb_mmu_fault_tu104.o \
+	hal/fb/intr/fb_intr_gv100.o \
+	hal/fb/intr/fb_intr_tu104.o \
+	hal/func/func_tu104.o \
+	hal/fifo/fifo_tu104.o \
+	hal/fifo/usermode_tu104.o \
+	hal/fifo/pbdma_tu104.o \
+	hal/fifo/ramfc_tu104.o \
+	hal/fifo/ramin_tu104.o \
+	hal/fifo/channel_gv100.o \
+	hal/fifo/runlist_ram_tu104.o \
+	hal/fifo/runlist_fifo_gv100.o \
+	hal/fifo/runlist_fifo_tu104.o \
+	hal/fifo/fifo_intr_gv100.o \
+	hal/fuse/fuse_gp106.o \
+	hal/netlist/netlist_gv100.o \
+	hal/netlist/netlist_tu104.o \
+	hal/nvdec/nvdec_gp106.o \
+	hal/nvdec/nvdec_tu104.o \
+	hal/gsp/gsp_tu104.o \
+	hal/sec2/sec2_tu104.o \
+	hal/pramin/pramin_gp10b.o \
+	hal/pramin/pramin_gv100.o \
+	hal/pramin/pramin_init.o \
+	hal/pramin/pramin_tu104.o \
+	hal/bios/bios_tu104.o \
+	hal/top/top_gv100.o \
+	hal/xve/xve_gp106.o \
+	hal/xve/xve_tu104.o
+
+nvgpu-$(CONFIG_DEBUG_FS) += \
+	os/linux/debug_therm_tu104.o \
+	os/linux/debug_bios.o \
+	os/linux/debug_xve.o \
+	os/linux/debug_clk_tu104.o
+endif
+
+# nvlink sources are not conditionally compiled. nvlink probe and
+# public functions return -ENODEV when not supported.
+
+nvgpu-y += \
+	common/vbios/nvlink_bios.o \
+	common/nvlink/probe.o \
+	common/nvlink/init/device_reginit.o \
+	common/nvlink/init/device_reginit_gv100.o \
+	common/nvlink/intr_and_err_handling_gv100.o \
+	common/nvlink/minion.o \
+	common/nvlink/link_mode_transitions.o \
+	common/nvlink/nvlink_gv100.o \
+	common/nvlink/nvlink_tu104.o \
+	common/nvlink/nvlink.o \
+	os/linux/nvlink_probe.o \
+	os/linux/nvlink.o \
+	hal/nvlink/minion_gv100.o \
+	hal/nvlink/minion_tu104.o \
+	hal/nvlink/link_mode_transitions_gv100.o \
+	hal/nvlink/link_mode_transitions_tu104.o
+
+nvgpu-$(CONFIG_GK20A_PCI) += \
+	os/linux/pci.o \
+	os/linux/pci_power.o
+
 nvgpu-y += \
 	common/utils/enabled.o \
 	common/utils/rbtree.o \
@@ -138,7 +237,6 @@ nvgpu-y += \
 	common/acr/acr_sw_gm20b.o \
 	common/acr/acr_sw_gp10b.o \
 	common/acr/acr_sw_gv11b.o \
-	common/acr/acr_sw_tu104.o \
 	common/sbr/sbr.o \
 	common/pmu/super_surface/super_surface.o \
 	common/pmu/lsfm/lsfm.o \
@@ -179,27 +277,11 @@ nvgpu-y += \
 	common/pmu/boardobj/boardobjgrp_e32.o \
 	common/clk_arb/clk_arb.o \
 	common/clk_arb/clk_arb_gp10b.o \
-	common/clk_arb/clk_arb_gv100.o \
-	common/nvlink/probe.o \
-	common/nvlink/init/device_reginit_gv100.o \
-	common/nvlink/init/device_reginit.o \
-	common/nvlink/intr_and_err_handling_gv100.o \
-	common/nvlink/minion.o \
-	common/nvlink/link_mode_transitions.o \
-	common/nvlink/nvlink.o \
-	common/nvlink/nvlink_gv100.o \
-	common/nvlink/nvlink_tu104.o \
 	common/rc/rc.o \
-	hal/mc/mc_gv100.o \
-	hal/mc/mc_tu104.o \
 	hal/bus/bus_gk20a.o \
-	hal/bus/bus_gv100.o \
-	hal/bus/bus_tu104.o \
 	hal/class/class_gm20b.o \
 	hal/class/class_gp10b.o \
-	hal/class/class_tu104.o \
 	hal/clk/clk_gm20b.o \
-	hal/clk/clk_tu104.o \
 	hal/gr/ecc/ecc_gp10b.o \
 	hal/gr/ecc/ecc_gv11b.o \
 	hal/gr/zcull/zcull_gm20b.o \
@@ -208,12 +290,9 @@ nvgpu-y += \
 	hal/gr/ctxsw_prog/ctxsw_prog_gv11b.o \
 	hal/gr/init/gr_init_gm20b.o \
 	hal/gr/init/gr_init_gp10b.o \
-	hal/gr/init/gr_init_gv100.o \
 	hal/gr/init/gr_init_gv11b.o \
-	hal/gr/init/gr_init_tu104.o \
 	hal/gr/intr/gr_intr_gm20b.o \
 	hal/gr/intr/gr_intr_gp10b.o \
-	hal/gr/intr/gr_intr_tu104.o \
 	hal/gr/hwpm_map/hwpm_map_gv100.o \
 	hal/gr/zbc/zbc_gm20b.o \
 	hal/gr/zbc/zbc_gp10b.o \
@@ -224,14 +303,12 @@ nvgpu-y += \
 	hal/gr/gr/gr_gv100.o \
 	hal/gr/gr/gr_gv11b.o \
 	hal/gr/gr/gr_tu104.o \
-	hal/fbpa/fbpa_tu104.o \
 	hal/init/hal_gv11b.o \
 	hal/init/hal_gv11b_litter.o \
 	hal/init/hal_init.o \
 	hal/perf/perf_gv11b.o \
 	hal/power_features/cg/gp10b_gating_reglist.o \
 	hal/power_features/cg/gv11b_gating_reglist.o \
-	hal/power_features/cg/tu104_gating_reglist.o \
 	hal/regops/regops_gv11b.o \
 	hal/ce/ce2_gk20a.o \
 	hal/therm/therm_gp10b.o \
@@ -239,56 +316,28 @@ nvgpu-y += \
 	hal/gr/falcon/gr_falcon_gm20b.o \
 	hal/ltc/ltc_gp10b.o \
 	hal/ltc/ltc_gv11b.o  \
-	hal/ltc/ltc_tu104.o \
 	hal/ltc/intr/ltc_intr_gm20b.o \
 	hal/ltc/intr/ltc_intr_gp10b.o \
 	hal/fb/fb_gm20b.o \
 	hal/fb/fb_gp10b.o \
 	hal/fb/fb_gp106.o \
 	hal/fb/fb_gv11b.o \
-	hal/fb/fb_gv100.o \
-	hal/fb/fb_tu104.o \
-	hal/fb/fb_mmu_fault_tu104.o \
 	hal/fb/intr/fb_intr_ecc_gv11b.o \
-	hal/fb/intr/fb_intr_gv100.o \
-	hal/fb/intr/fb_intr_tu104.o \
 	hal/fuse/fuse_gm20b.o \
-	hal/fuse/fuse_gp106.o \
-	hal/func/func_tu104.o \
 	hal/fifo/fifo_gk20a.o \
-	hal/fifo/fifo_tu104.o \
 	hal/fifo/preempt_gk20a.o \
-	hal/fifo/usermode_tu104.o \
-	hal/fifo/pbdma_tu104.o \
 	hal/fifo/ramfc_gk20a.o \
 	hal/fifo/ramfc_gp10b.o \
-	hal/fifo/ramfc_tu104.o \
 	hal/fifo/ramin_gk20a.o \
-	hal/fifo/ramin_tu104.o \
-	hal/fifo/runlist_ram_tu104.o \
 	hal/fifo/runlist_fifo_gv11b.o \
-	hal/fifo/runlist_fifo_gv100.o \
-	hal/fifo/runlist_fifo_tu104.o \
 	hal/fifo/channel_gk20a.o \
 	hal/fifo/channel_gm20b.o \
-	hal/fifo/channel_gv100.o \
 	hal/fifo/tsg_gk20a.o \
 	hal/fifo/userd_gk20a.o \
 	hal/fifo/userd_gv11b.o \
 	hal/fifo/fifo_intr_gk20a.o \
-	hal/fifo/fifo_intr_gv100.o \
 	hal/fifo/ctxsw_timeout_gk20a.o \
 	hal/netlist/netlist_gp10b.o \
-	hal/netlist/netlist_gv100.o \
-	hal/netlist/netlist_tu104.o \
-	hal/nvdec/nvdec_gp106.o \
-	hal/nvdec/nvdec_tu104.o \
-	hal/nvlink/minion_gv100.o \
-	hal/nvlink/minion_tu104.o \
-	hal/nvlink/link_mode_transitions_gv100.o \
-	hal/nvlink/link_mode_transitions_tu104.o \
-	hal/gsp/gsp_tu104.o \
-	hal/sec2/sec2_tu104.o \
 	hal/sync/sema_cmdbuf_gk20a.o \
 	hal/sync/sema_cmdbuf_gv11b.o \
 	hal/pmu/pmu_gk20a.o \
@@ -296,25 +345,15 @@ nvgpu-y += \
 	hal/pmu/pmu_gp10b.o \
 	hal/pmu/pmu_gv11b.o \
 	hal/pmu/pmu_tu104.o \
-	hal/pramin/pramin_gp10b.o \
-	hal/pramin/pramin_gv100.o \
-	hal/pramin/pramin_init.o \
-	hal/pramin/pramin_tu104.o \
-	hal/bios/bios_tu104.o \
 	hal/top/top_gp106.o \
 	hal/top/top_gp10b.o \
-	hal/top/top_gv100.o \
+	hal/tpc/tpc_gv11b.o
-	hal/tpc/tpc_gv11b.o \
-	hal/xve/xve_gp106.o \
-	hal/xve/xve_tu104.o
-
 
 # Linux specific parts of nvgpu.
 nvgpu-y += \
 	os/linux/os_ops.o \
 	os/linux/os_ops_gm20b.o \
 	os/linux/os_ops_gp10b.o \
-	os/linux/os_ops_gv100.o \
 	os/linux/os_ops_gv11b.o \
 	os/linux/kmem.o \
 	os/linux/timers.o \
@@ -343,15 +382,12 @@ nvgpu-y += \
 	os/linux/sim.o \
 	os/linux/sim_pci.o \
 	os/linux/os_sched.o \
-	os/linux/nvlink_probe.o \
-	os/linux/nvlink.o \
 	os/linux/dt.o \
 	os/linux/ecc_sysfs.o \
-	os/linux/os_ops_tu104.o \
 	os/linux/bsearch.o \
-	os/linux/sdl/sdl_stub.o \
+	os/linux/sdl/sdl_stub.o
-	os/linux/dmabuf_vidmem.o \
+
-	os/linux/vpr.o
+nvgpu-$(CONFIG_NVGPU_VPR) += os/linux/vpr.o
 
 nvgpu-$(CONFIG_NVGPU_DMABUF_HAS_DRVDATA) += os/linux/dmabuf_priv.o
 
@@ -366,11 +402,7 @@ nvgpu-$(CONFIG_DEBUG_FS) += \
 	os/linux/debug_allocator.o \
 	os/linux/debug_hal.o \
 	os/linux/debug_clk_gm20b.o \
-	os/linux/debug_therm_tu104.o \
-	os/linux/debug_bios.o \
 	os/linux/debug_ltc.o \
-	os/linux/debug_xve.o \
-	os/linux/debug_clk_tu104.o \
 	os/linux/debug_volt.o \
 	os/linux/debug_s_param.o
 
@@ -413,10 +445,6 @@ nvgpu-$(CONFIG_SYNC) += \
 nvgpu-y += common/sync/channel_sync_syncpt.o
 endif
 
-nvgpu-$(CONFIG_GK20A_PCI) += \
-	os/linux/pci.o \
-	os/linux/pci_power.o
-
 nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += \
 	os/linux/nvhost.o \
 	hal/sync/syncpt_cmdbuf_gk20a.o \
@@ -455,7 +483,6 @@ nvgpu-y += \
 	common/mm/allocators/nvgpu_allocator.o \
 	common/mm/allocators/bitmap_allocator.o \
 	common/mm/allocators/buddy_allocator.o \
-	common/mm/allocators/page_allocator.o \
 	common/mm/allocators/lockless_allocator.o \
 	common/mm/gmmu/page_table.o \
 	common/mm/gmmu/pd_cache.o \
@@ -466,26 +493,12 @@ nvgpu-y += \
 	common/mm/nvgpu_sgt.o \
 	common/mm/mm.o \
 	common/mm/dma.o \
-	common/mm/vidmem.o \
-	common/pramin.o \
 	common/vbios/bios.o \
-	common/vbios/nvlink_bios.o \
-	common/vbios/bios_sw_gv100.o \
-	common/vbios/bios_sw_tu104.o \
 	common/falcon/falcon.o \
 	common/falcon/falcon_sw_gk20a.o \
-	common/falcon/falcon_sw_tu104.o \
 	common/engine_queues/engine_mem_queue.o \
 	common/engine_queues/engine_dmem_queue.o \
-	common/engine_queues/engine_emem_queue.o \
 	common/engine_queues/engine_fb_queue.o \
-	common/sec2/sec2.o \
-	common/sec2/sec2_allocator.o \
-	common/sec2/sec2_lsfm.o \
-	common/sec2/ipc/sec2_cmd.o \
-	common/sec2/ipc/sec2_msg.o \
-	common/sec2/ipc/sec2_queue.o \
-	common/sec2/ipc/sec2_seq.o \
 	common/io/io.o \
 	common/power_features/power_features.o \
 	common/power_features/cg/cg.o \
@@ -508,7 +521,6 @@ nvgpu-y += \
 	common/ecc.o \
 	common/log_common.o \
 	common/ce/ce.o \
-	common/ce/ce_app.o \
 	common/debugger.o
 
 nvgpu-$(CONFIG_NVGPU_GR_VIRTUALIZATION) += \
@@ -659,8 +671,6 @@ nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
 	hal/init/hal_gp10b_litter.o \
 	hal/init/hal_gm20b.o \
 	hal/init/hal_gm20b_litter.o \
-	hal/init/hal_tu104.o \
-	hal/init/hal_tu104_litter.o \
 	hal/fifo/engine_status_gm20b.o \
 	hal/fifo/engines_gm20b.o \
 	hal/fifo/pbdma_gm20b.o \
@@ -682,8 +692,6 @@ nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
 	hal/mm/cache/flush_gk20a.o \
 	hal/mm/mm_gm20b.o \
 	hal/mm/mm_gk20a.o \
-	hal/mm/mm_gv100.o \
-	hal/mm/mm_tu104.o \
 	hal/mm/gmmu/gmmu_gk20a.o \
 	hal/mm/gmmu/gmmu_gm20b.o \
 	hal/falcon/falcon_gk20a.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -37,8 +37,11 @@ srcs +=	os/posix/nvgpu.c \
 	os/posix/stubs.c \
 	os/posix/posix-nvhost.c \
 	os/posix/posix-vgpu.c \
-	os/posix/posix-dt.c \
+	os/posix/posix-dt.c
-	os/posix/posix-vpr.c
+
+ifdef CONFIG_NVGPU_VPR
+srcs += os/posix/posix-vpr.c
+endif
 
 ifdef CONFIG_NVGPU_FECS_TRACE
 srcs += os/posix/fecs_trace_posix.c

drivers/gpu/nvgpu/common/vbios/bios.c

@@ -180,6 +180,7 @@ int nvgpu_bios_sw_init(struct gk20a *g)
 	}
 
 	switch (ver) {
+#ifdef CONFIG_NVGPU_DGPU
 	case NVGPU_GPUID_GV100:
 		nvgpu_gv100_bios_sw_init(g, g->bios);
 		break;
@@ -187,6 +188,7 @@ int nvgpu_bios_sw_init(struct gk20a *g)
 	case NVGPU_GPUID_TU104:
 		nvgpu_tu104_bios_sw_init(g, g->bios);
 		break;
+#endif
 	default:
 		goto clean_bios;
 	}

drivers/gpu/nvgpu/include/nvgpu/vpr.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,13 @@
 
 #include <nvgpu/types.h>
 
+#ifdef CONFIG_NVGPU_VPR
 bool nvgpu_is_vpr_resize_enabled(void);
+#else
+static inline bool nvgpu_is_vpr_resize_enabled(void)
+{
+	return false;
+}
+#endif
 
 #endif /* NVGPU_VPR_H */

drivers/gpu/nvgpu/os/linux/debug.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2019 NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2017-2020 NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -430,10 +430,12 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
 	nvgpu_kmem_debugfs_init(g);
 #endif
 	nvgpu_ltc_debugfs_init(g);
+#ifdef CONFIG_NVGPU_DGPU
 	if (g->pci_vendor_id) {
 		nvgpu_xve_debugfs_init(g);
 		nvgpu_bios_debugfs_init(g);
 	}
+#endif
 }
 
 void gk20a_debug_deinit(struct gk20a *g)

drivers/gpu/nvgpu/os/linux/dmabuf.c

@@ -34,6 +34,7 @@
 enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g,
 					  struct dma_buf *dmabuf)
 {
+#ifdef CONFIG_NVGPU_DGPU
 	struct gk20a *buf_owner = nvgpu_vidmem_buf_owner(dmabuf);
 	bool unified_memory = nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY);
 
@@ -49,12 +50,12 @@ enum nvgpu_aperture gk20a_dmabuf_aperture(struct gk20a *g,
 	} else if (buf_owner != g) {
 		/* Someone else's vidmem */
 		return APERTURE_INVALID;
-	}
+	} else {
-#ifdef CONFIG_NVGPU_DGPU
-	else {
 		/* Yay, buf_owner == g */
 		return APERTURE_VIDMEM;
 	}
+#else
+	return APERTURE_SYSMEM;
 #endif
 }
 

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -322,7 +322,13 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 
 	gpu.bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */
 
+#ifdef CONFIG_NVGPU_COMPRESSION
 	gpu.compression_page_size = g->ops.fb.compression_page_size(g);
+	gpu.gr_compbit_store_base_hw = g->cbc->compbit_store.base_hw;
+	gpu.gr_gobs_per_comptagline_per_slice =
+		g->cbc->gobs_per_comptagline_per_slice;
+	gpu.cbc_comptags_per_line = g->cbc->comptags_per_cacheline;
+#endif
 
 	gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g);
 
@@ -377,20 +383,18 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.fbp_en_mask = nvgpu_fbp_get_fbp_en_mask(g->fbp);;
 	gpu.max_ltc_per_fbp =  g->ops.top.get_max_ltc_per_fbp(g);
 	gpu.max_lts_per_ltc = g->ops.top.get_max_lts_per_ltc(g);
-	gpu.gr_compbit_store_base_hw = g->cbc->compbit_store.base_hw;
-	gpu.gr_gobs_per_comptagline_per_slice =
-		g->cbc->gobs_per_comptagline_per_slice;
 	gpu.num_ltc = nvgpu_ltc_get_ltc_count(g);
 	gpu.lts_per_ltc = nvgpu_ltc_get_slices_per_ltc(g);
 	gpu.cbc_cache_line_size = nvgpu_ltc_get_cacheline_size(g);
-	gpu.cbc_comptags_per_line = g->cbc->comptags_per_cacheline;
 
 	if ((g->ops.clk.get_maxrate) && nvgpu_platform_is_silicon(g)) {
 		gpu.max_freq = g->ops.clk.get_maxrate(g,
 				CTRL_CLK_DOMAIN_GPCCLK);
 	}
 
+#ifdef CONFIG_NVGPU_DGPU
 	gpu.local_video_memory_size = g->mm.vidmem.size;
+#endif
 
 	gpu.pci_vendor_id = g->pci_vendor_id;
 	gpu.pci_device_id = g->pci_device_id;
@@ -995,6 +999,7 @@ clean_up:
 	return err;
 }
 
+#ifdef CONFIG_NVGPU_DGPU
 static int nvgpu_gpu_alloc_vidmem(struct gk20a *g,
 			struct nvgpu_gpu_alloc_vidmem_args *args)
 {
@@ -1059,6 +1064,7 @@ static int nvgpu_gpu_get_memory_state(struct gk20a *g,
 
 	return err;
 }
+#endif
 
 static u32 nvgpu_gpu_convert_clk_domain(u32 clk_domain)
 {
@@ -1936,6 +1942,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
 			(struct nvgpu_gpu_get_engine_info_args *)buf);
 		break;
 
+#ifdef CONFIG_NVGPU_DGPU
 	case NVGPU_GPU_IOCTL_ALLOC_VIDMEM:
 		err = nvgpu_gpu_alloc_vidmem(g,
 			(struct nvgpu_gpu_alloc_vidmem_args *)buf);
@@ -1945,6 +1952,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
 		err = nvgpu_gpu_get_memory_state(g,
 			(struct nvgpu_gpu_get_memory_state_args *)buf);
 		break;
+#endif
 
 	case NVGPU_GPU_IOCTL_CLK_GET_RANGE:
 		err = nvgpu_gpu_clk_get_range(g, priv,

drivers/gpu/nvgpu/os/linux/ioctl_dbg.c

@@ -1,7 +1,7 @@
 /*
  * Tegra GK20A GPU Debugger/Profiler Driver
  *
- * Copyright (c) 2017-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -1565,6 +1565,7 @@ nvgpu_dbg_gpu_ioctl_suspend_resume_contexts(struct dbg_session_gk20a *dbg_s,
 	return err;
 }
 
+#ifdef CONFIG_NVGPU_DGPU
 static int nvgpu_dbg_gpu_ioctl_access_fb_memory(struct dbg_session_gk20a *dbg_s,
 		struct nvgpu_dbg_gpu_access_fb_memory_args *args)
 {
@@ -1643,6 +1644,7 @@ fail_dmabuf_put:
 
 	return err;
 }
+#endif
 
 static int nvgpu_ioctl_profiler_reserve(struct dbg_session_gk20a *dbg_s,
 			   struct nvgpu_dbg_gpu_profiler_reserve_args *args)
@@ -2123,10 +2125,12 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
 		      (struct nvgpu_dbg_gpu_suspend_resume_contexts_args *)buf);
 		break;
 
+#ifdef CONFIG_NVGPU_DGPU
 	case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY:
 		err = nvgpu_dbg_gpu_ioctl_access_fb_memory(dbg_s,
 			(struct nvgpu_dbg_gpu_access_fb_memory_args *)buf);
 		break;
+#endif
 
 	case NVGPU_DBG_GPU_IOCTL_PROFILER_ALLOCATE:
 		err = nvgpu_ioctl_allocate_profiler_object(dbg_s_linux,

drivers/gpu/nvgpu/os/linux/nvgpu_mem.c

@@ -25,6 +25,7 @@
 #include <nvgpu/vidmem.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/string.h>
+#include <nvgpu/nvgpu_sgt.h>
 #include <nvgpu/nvgpu_sgt_os.h>
 
 #include <nvgpu/linux/dma.h>
@@ -106,6 +107,7 @@ static u64 nvgpu_mem_get_addr_sysmem(struct gk20a *g, struct nvgpu_mem *mem)
  */
 u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem)
 {
+#ifdef CONFIG_NVGPU_DGPU
 	struct nvgpu_page_alloc *alloc;
 
 	if (mem->aperture == APERTURE_SYSMEM)
@@ -120,6 +122,12 @@ u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem)
 	WARN_ON(alloc->nr_chunks != 1);
 
 	return alloc->base;
+#else
+	if (mem->aperture == APERTURE_SYSMEM)
+		return nvgpu_mem_get_addr_sysmem(g, mem);
+
+	return 0;
+#endif
 }
 
 /*
@@ -274,6 +282,7 @@ static const struct nvgpu_sgt_ops nvgpu_linux_sgt_ops = {
 	.sgt_free      = nvgpu_mem_linux_sgl_free,
 };
 
+#ifdef CONFIG_NVGPU_DGPU
 static struct nvgpu_sgt *__nvgpu_mem_get_sgl_from_vidmem(
 	struct gk20a *g,
 	struct scatterlist *linux_sgl)
@@ -286,14 +295,17 @@ static struct nvgpu_sgt *__nvgpu_mem_get_sgl_from_vidmem(
 
 	return &vidmem_alloc->sgt;
 }
+#endif
 
 struct nvgpu_sgt *nvgpu_linux_sgt_create(struct gk20a *g, struct sg_table *sgt)
 {
 	struct nvgpu_sgt *nvgpu_sgt;
 	struct scatterlist *linux_sgl = sgt->sgl;
 
+#ifdef CONFIG_NVGPU_DGPU
 	if (nvgpu_addr_is_vidmem_page_alloc(sg_dma_address(linux_sgl)))
 		return __nvgpu_mem_get_sgl_from_vidmem(g, linux_sgl);
+#endif
 
 	nvgpu_sgt = nvgpu_kzalloc(g, sizeof(*nvgpu_sgt));
 	if (!nvgpu_sgt)

drivers/gpu/nvgpu/os/linux/os_ops.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -35,15 +35,17 @@ int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
 	case NVGPU_GPUID_GP10B:
 		nvgpu_gp10b_init_os_ops(l);
 		break;
-	case NVGPU_GPUID_GV100:
-		nvgpu_gv100_init_os_ops(l);
-		break;
 	case NVGPU_GPUID_GV11B:
 		nvgpu_gv11b_init_os_ops(l);
 		break;
+#ifdef CONFIG_NVGPU_DGPU
+	case NVGPU_GPUID_GV100:
+		nvgpu_gv100_init_os_ops(l);
+		break;
 	case NVGPU_GPUID_TU104:
 		nvgpu_tu104_init_os_ops(l);
 		break;
+#endif
 	default:
 		break;
 	}

drivers/gpu/nvgpu/os/linux/vm.c

@@ -23,6 +23,7 @@
 #include <nvgpu/rbtree.h>
 #include <nvgpu/vm_area.h>
 #include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/nvgpu_sgt.h>
 #include <nvgpu/page_allocator.h>
 #include <nvgpu/vidmem.h>
 #include <nvgpu/utils.h>