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gpu: nvgpu: Rename gk20a_mem_* functions

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Rename the functions used for mem_desc access to nvgpu_mem_*.

JIRA NVGPU-12

Change-Id: I5a1180c9a08d33c3dfc361ce8579c3c767fa5656
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1326193
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2017-03-22 10:00:24 -07:00
committed by mobile promotions
parent 2766420dfb
commit 633d331ae2
3 changed files with 53 additions and 53 deletions
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32
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -117,20 +117,20 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
gk20a_dbg_fn("");
gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v());
nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v());
gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(),
nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(),
pbdma_gp_base_offset_f(
u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(),
pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
gk20a_mem_wr32(g, mem, ram_fc_signature_w(),
nvgpu_mem_wr32(g, mem, ram_fc_signature_w(),
c->g->ops.fifo.get_pbdma_signature(c->g));
gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(),
nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(),
pbdma_pb_header_priv_user_f() |
pbdma_pb_header_method_zero_f() |
pbdma_pb_header_subchannel_zero_f() |
@@ -138,44 +138,44 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
pbdma_pb_header_first_true_f() |
pbdma_pb_header_type_inc_f());
gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(),
nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(),
pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) |
pbdma_subdevice_status_active_f() |
pbdma_subdevice_channel_dma_enable_f());
gk20a_mem_wr32(g, mem, ram_fc_target_w(),
nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
pbdma_target_eng_ctx_valid_true_f() |
pbdma_target_ce_ctx_valid_true_f() |
pbdma_target_engine_sw_f());
gk20a_mem_wr32(g, mem, ram_fc_acquire_w(),
nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
g->ops.fifo.pbdma_acquire_val(acquire_timeout));
gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
pbdma_runlist_timeslice_timeout_128_f() |
pbdma_runlist_timeslice_timescale_3_f() |
pbdma_runlist_timeslice_enable_true_f());
gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
/* Until full subcontext is supported, always use VEID0 */
gk20a_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
pbdma_set_channel_info_scg_type_graphics_compute0_f() |
pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0));
if (c->is_privileged_channel) {
/* Set privilege level for channel */
gk20a_mem_wr32(g, mem, ram_fc_config_w(),
nvgpu_mem_wr32(g, mem, ram_fc_config_w(),
pbdma_config_auth_level_privileged_f());
gk20a_fifo_setup_ramfc_for_privileged_channel(c);
}
/* Enable userd writeback */
data = gk20a_mem_rd32(g, mem, ram_fc_config_w());
data = nvgpu_mem_rd32(g, mem, ram_fc_config_w());
data = data | pbdma_config_userd_writeback_enable_f();
gk20a_mem_wr32(g, mem, ram_fc_config_w(),data);
nvgpu_mem_wr32(g, mem, ram_fc_config_w(),data);
gv11b_userd_writeback_config(g);
@@ -196,7 +196,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c)
struct mem_desc *userd_mem = &g->fifo.userd;
u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32));
return gk20a_mem_rd32(g, userd_mem,
return nvgpu_mem_rd32(g, userd_mem,
offset + ram_userd_gp_get_w());
}
@@ -205,7 +205,7 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c)
struct mem_desc *userd_mem = &g->fifo.userd;
u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32));
gk20a_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(),
nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(),
c->gpfifo.put);
/* commit everything to cpu */
smp_mb();

50
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -780,36 +780,36 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
{
struct mem_desc *mem = &gr_ctx->mem;
if (gk20a_mem_begin(g, mem)) {
if (nvgpu_mem_begin(g, mem)) {
WARN_ON("Cannot map context");
return;
}
gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n",
gk20a_mem_rd(g, mem,
nvgpu_mem_rd(g, mem,
ctxsw_prog_main_image_magic_value_o()),
ctxsw_prog_main_image_magic_value_v_value_v());
gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n",
gk20a_mem_rd(g, mem,
nvgpu_mem_rd(g, mem,
ctxsw_prog_main_image_num_save_ops_o()));
gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n",
gk20a_mem_rd(g, mem,
nvgpu_mem_rd(g, mem,
ctxsw_prog_main_image_num_wfi_save_ops_o()));
gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n",
gk20a_mem_rd(g, mem,
nvgpu_mem_rd(g, mem,
ctxsw_prog_main_image_num_cta_save_ops_o()));
gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n",
gk20a_mem_rd(g, mem,
nvgpu_mem_rd(g, mem,
ctxsw_prog_main_image_num_gfxp_save_ops_o()));
gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n",
gk20a_mem_rd(g, mem,
nvgpu_mem_rd(g, mem,
ctxsw_prog_main_image_num_cilp_save_ops_o()));
gk20a_err(dev_from_gk20a(g),
"image gfx preemption option (GFXP is 1) %x\n",
gk20a_mem_rd(g, mem,
nvgpu_mem_rd(g, mem,
ctxsw_prog_main_image_graphics_preemption_options_o()));
gk20a_mem_end(g, mem);
nvgpu_mem_end(g, mem);
}
static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
@@ -847,13 +847,13 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) {
gk20a_dbg_info("GfxP: %x", gfxp_preempt_option);
gk20a_mem_wr(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o(),
nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o(),
gfxp_preempt_option);
}
if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) {
gk20a_dbg_info("CILP: %x", cilp_preempt_option);
gk20a_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(),
nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(),
cilp_preempt_option);
}
@@ -862,7 +862,7 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
u32 size;
u32 cbes_reserve;
gk20a_mem_wr(g, mem, ctxsw_prog_main_image_full_preemption_ptr_o(),
nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_full_preemption_ptr_o(),
gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8);
err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
@@ -1858,12 +1858,12 @@ static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
addr_hi = u64_hi32(ctx->mem.gpu_va);
/* point this address to engine_wfi_ptr */
gk20a_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(),
nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(),
ram_in_engine_cs_wfi_v() |
ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) |
ram_in_engine_wfi_ptr_lo_f(addr_lo));
gk20a_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_ptr_hi_w(),
nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_ptr_hi_w(),
ram_in_engine_wfi_ptr_hi_f(addr_hi));
return 0;
@@ -1930,20 +1930,20 @@ static void gv11b_restore_context_header(struct gk20a *g,
u32 va_lo, va_hi;
struct gr_gk20a *gr = &g->gr;
va_hi = gk20a_mem_rd(g, ctxheader,
va_hi = nvgpu_mem_rd(g, ctxheader,
ctxsw_prog_main_image_context_buffer_ptr_hi_o());
va_lo = gk20a_mem_rd(g, ctxheader,
va_lo = nvgpu_mem_rd(g, ctxheader,
ctxsw_prog_main_image_context_buffer_ptr_o());
gk20a_mem_wr_n(g, ctxheader, 0,
nvgpu_mem_wr_n(g, ctxheader, 0,
gr->ctx_vars.local_golden_image,
gr->ctx_vars.golden_image_size);
gk20a_mem_wr(g, ctxheader,
nvgpu_mem_wr(g, ctxheader,
ctxsw_prog_main_image_context_buffer_ptr_hi_o(), va_hi);
gk20a_mem_wr(g, ctxheader,
nvgpu_mem_wr(g, ctxheader,
ctxsw_prog_main_image_context_buffer_ptr_o(), va_lo);
gk20a_mem_wr(g, ctxheader,
nvgpu_mem_wr(g, ctxheader,
ctxsw_prog_main_image_num_restore_ops_o(), 0);
gk20a_mem_wr(g, ctxheader,
nvgpu_mem_wr(g, ctxheader,
ctxsw_prog_main_image_num_save_ops_o(), 0);
}
static void gr_gv11b_write_zcull_ptr(struct gk20a *g,
@@ -1954,9 +1954,9 @@ static void gr_gv11b_write_zcull_ptr(struct gk20a *g,
gpu_va = gpu_va >> 8;
va_lo = u64_lo32(gpu_va);
va_hi = u64_hi32(gpu_va);
gk20a_mem_wr(g, mem,
nvgpu_mem_wr(g, mem,
ctxsw_prog_main_image_zcull_ptr_o(), va_lo);
gk20a_mem_wr(g, mem,
nvgpu_mem_wr(g, mem,
ctxsw_prog_main_image_zcull_ptr_hi_o(), va_hi);
}
@@ -1969,9 +1969,9 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g,
gpu_va = gpu_va >> 8;
va_lo = u64_lo32(gpu_va);
va_hi = u64_hi32(gpu_va);
gk20a_mem_wr(g, mem,
nvgpu_mem_wr(g, mem,
ctxsw_prog_main_image_pm_ptr_o(), va_lo);
gk20a_mem_wr(g, mem,
nvgpu_mem_wr(g, mem,
ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi);
}

24
drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
View File

@@ -73,11 +73,11 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c)
return -ENOMEM;
}
/* Now clear the buffer */
if (gk20a_mem_begin(g, &ctx->mem))
if (nvgpu_mem_begin(g, &ctx->mem))
return -ENOMEM;
gk20a_memset(g, &ctx->mem, 0, 0, ctx->mem.size);
gk20a_mem_end(g, &ctx->mem);
nvgpu_memset(g, &ctx->mem, 0, 0, ctx->mem.size);
nvgpu_mem_end(g, &ctx->mem);
gv11b_init_subcontext_pdb(c, &c->inst_block);
@@ -111,14 +111,14 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c,
ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
lo = ram_in_sc_page_dir_base_vol_0_w();
hi = ram_in_sc_page_dir_base_hi_0_w();
gk20a_mem_wr32(g, inst_block, lo, format_word);
gk20a_mem_wr32(g, inst_block, hi, pdb_addr_hi);
nvgpu_mem_wr32(g, inst_block, lo, format_word);
nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi);
/* make subcontext0 address space to valid */
/* TODO fix proper hw register definations */
gk20a_mem_wr32(g, inst_block, 166, 0x1);
gk20a_mem_wr32(g, inst_block, 167, 0);
gk20a_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(),
nvgpu_mem_wr32(g, inst_block, 166, 0x1);
nvgpu_mem_wr32(g, inst_block, 167, 0);
nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(),
ram_in_engine_wfi_veid_f(0));
}
@@ -136,13 +136,13 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va)
gr_mem = &ctx->mem;
g->ops.mm.l2_flush(g, true);
if (gk20a_mem_begin(g, gr_mem))
if (nvgpu_mem_begin(g, gr_mem))
return -ENOMEM;
gk20a_mem_wr(g, gr_mem,
nvgpu_mem_wr(g, gr_mem,
ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi);
gk20a_mem_wr(g, gr_mem,
nvgpu_mem_wr(g, gr_mem,
ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo);
gk20a_mem_end(g, gr_mem);
nvgpu_mem_end(g, gr_mem);
return ret;
}