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gpu: nvgpu: Fix MISRA 12.2 misc bit shift errors

Browse Source 
MISRA rule 12.2 states that the right hand operand of a shift
operator shall lie in the range zero to one less than the width
in bits of the essential type of the left hand operand. This
patch will fix these violations by casting them to an appropriate
type or using the relevant BITxx() macros.

JIRA NVGPU-666

Change-Id: I57b6081e9bd98c45ca9f7aa5f35e1d2d66ed0134
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945655
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Srirangan Madhavan
2018-11-08 16:30:51 +05:30
committed by mobile promotions
parent 9c982aba65
commit 63d1b7113a
13 changed files with 51 additions and 40 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/fifo/channel.c
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@@ -137,13 +137,13 @@ int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g,
unsigned int shift = 0;
/* value field is 8 bits long */
while (value >= 1 << 8) {
while (value >= BIT32(8)) {
value >>= 1;
shift++;
}
/* time slice register is only 18bits long */
if ((value << shift) >= 1<<19) {
if ((value << shift) >= BIT32(19)) {
nvgpu_err(g, "Requested timeslice value is clamped to 18 bits\n");
value = 255;
shift = 10;

2
drivers/gpu/nvgpu/common/pmu/pmu.c
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@@ -603,7 +603,7 @@ void nvgpu_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
fb->address.lo = u64_lo32(mem->gpu_va);
fb->address.hi = u64_hi32(mem->gpu_va);
fb->params = ((u32)mem->size & 0xFFFFFFU);
fb->params |= (GK20A_PMU_DMAIDX_VIRT << 24);
fb->params |= (GK20A_PMU_DMAIDX_VIRT << 24U);
}
int nvgpu_pmu_vidmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,

4
drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
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@@ -170,7 +170,7 @@ static inline unsigned int gk20a_ce_get_method_size(int request_operation,
shift = (MAX_CE_ALIGN(chunk) != 0ULL) ?
__ffs(MAX_CE_ALIGN(chunk)) : MAX_CE_SHIFT;
width = chunk >> shift;
height = 1 << shift;
height = BIT32(shift);
width = MAX_CE_ALIGN(width);
chunk -= (u64) height * width;
@@ -244,7 +244,7 @@ int gk20a_ce_prepare_submit(u64 src_buf,
shift = (MAX_CE_ALIGN(chunk) != 0ULL) ?
__ffs(MAX_CE_ALIGN(chunk)) : MAX_CE_SHIFT;
height = chunk >> shift;
width = 1 << shift;
width = BIT32(shift);
height = MAX_CE_ALIGN(height);
chunk_size = (u64) height * width;

2
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -859,7 +859,7 @@ int gk20a_init_fifo_setup_sw_common(struct gk20a *g)
f->num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
f->userd_entry_size = 1 << ram_userd_base_shift_v();
f->userd_entry_size = BIT16(ram_userd_base_shift_v());
f->channel = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->channel));
f->tsg = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->tsg));

18
drivers/gpu/nvgpu/gk20a/mm_gk20a.c
View File

@@ -214,7 +214,13 @@ static void __update_pte(struct vm_gk20a *vm,
u32 addr = attrs->aperture == APERTURE_SYSMEM ?
gmmu_pte_address_sys_f(phys_shifted) :
gmmu_pte_address_vid_f(phys_shifted);
int ctag_shift = ilog2(g->ops.fb.compression_page_size(g));
int ctag_shift = 0;
int shamt = ilog2(g->ops.fb.compression_page_size(g));
if (shamt < 0) {
nvgpu_err(g, "shift amount 'shamt' is negative");
} else {
ctag_shift = shamt;
}
pte_w[0] = pte_valid | addr;
@@ -233,7 +239,7 @@ static void __update_pte(struct vm_gk20a *vm,
vm->mm->use_full_comp_tag_line &&
((phys_addr & 0x10000ULL) != 0ULL)) {
pte_w[1] |= gmmu_pte_comptagline_f(
1 << (gmmu_pte_comptagline_s() - 1U));
BIT32(gmmu_pte_comptagline_s() - 1U));
}
if (attrs->rw_flag == gk20a_mem_flag_read_only) {
@@ -264,7 +270,13 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
u32 page_size = vm->gmmu_page_sizes[attrs->pgsz];
u32 pd_offset = pd_offset_from_index(l, pd_idx);
u32 pte_w[2] = {0, 0};
int ctag_shift = ilog2(g->ops.fb.compression_page_size(g));
int ctag_shift = 0;
int shamt = ilog2(g->ops.fb.compression_page_size(g));
if (shamt < 0) {
nvgpu_err(g, "shift amount 'shamt' is negative");
} else {
ctag_shift = shamt;
}
if (phys_addr != 0ULL) {
__update_pte(vm, pte_w, phys_addr, attrs);

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -580,7 +580,7 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth);
zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3));
zbc_z &= ~(0x7f << (index % 4) * 7);
zbc_z &= ~(U32(0x7f) << (index % 4U) * 7U);
zbc_z |= depth_val->format << (index % 4) * 7;
gk20a_writel(g, zbc_z_format_reg + (index & ~3), zbc_z);

2
drivers/gpu/nvgpu/gp10b/mm_gp10b.c
View File

@@ -53,7 +53,7 @@ int gp10b_init_bar2_vm(struct gk20a *g)
u32 big_page_size = g->ops.mm.get_default_big_page_size();
/* BAR2 aperture size is 32MB */
mm->bar2.aperture_size = 32 << 20;
mm->bar2.aperture_size = U32(32) << 20U;
nvgpu_log_info(g, "bar2 vm size = 0x%x", mm->bar2.aperture_size);
mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K,

4
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -1878,12 +1878,12 @@ void gv11b_fifo_add_sema_cmd(struct gk20a *g,
if (acquire) {
/* sema_execute : acq_strict_geq | switch_en | 32bit */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2 | (1 << 12));
nvgpu_mem_wr32(g, cmd->mem, off++, U32(0x2) | BIT32(12));
} else {
/* sema_execute : release | wfi | 32bit */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
nvgpu_mem_wr32(g, cmd->mem, off++,
0x1 | ((wfi ? 0x1 : 0x0) << 20));
U32(0x1) | ((wfi ? U32(0x1) : U32(0x0)) << 20U));
/* non_stall_int : payload is ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008);

10
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1092,7 +1092,7 @@ int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr,
gk20a_writel(g, gr_gpcs_swdx_dss_zbc_s_r(index), stencil_val->depth);
zbc_s = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
(index & ~3));
zbc_s &= ~(0x7f << (index % 4) * 7);
zbc_s &= ~(U32(0x7f) << (index % 4U) * 7U);
zbc_s |= stencil_val->format << (index % 4) * 7;
gk20a_writel(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() +
(index & ~3), zbc_s);
@@ -2663,13 +2663,13 @@ int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr)
i++, j = j + 4) {
gk20a_writel(g, gr_ppcs_wwdx_map_table_cfg_coeff_r(i),
gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(
((1 << j) % gr->tpc_count)) |
(BIT32(j) % gr->tpc_count)) |
gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(
((1 << (j + 1)) % gr->tpc_count)) |
(BIT32(j + 1U) % gr->tpc_count)) |
gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(
((1 << (j + 2)) % gr->tpc_count)) |
(BIT32(j + 2U) % gr->tpc_count)) |
gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(
((1 << (j + 3)) % gr->tpc_count)));
(BIT32(j + 3U) % gr->tpc_count)));
}
gk20a_writel(g, gr_rstr2d_map_table_cfg_r(),

20
drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h
View File

@@ -30,21 +30,21 @@
*/
/* Broadcast PMM defines */
#define NV_PERF_PMMFBP_FBPGS_LTC 0x00250800
#define NV_PERF_PMMFBP_FBPGS_ROP 0x00250A00
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA 0x00250000
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB 0x00250200
#define NV_PERF_PMMGPC_GPCS 0x00278000
#define NV_PERF_PMMFBP_FBPS 0x0027C000
#define NV_PERF_PMMFBP_FBPGS_LTC 0x00250800U
#define NV_PERF_PMMFBP_FBPGS_ROP 0x00250A00U
#define NV_PERF_PMMGPC_GPCGS_GPCTPCA 0x00250000U
#define NV_PERF_PMMGPC_GPCGS_GPCTPCB 0x00250200U
#define NV_PERF_PMMGPC_GPCS 0x00278000U
#define NV_PERF_PMMFBP_FBPS 0x0027C000U
#define PRI_PMMGS_ADDR_WIDTH 9
#define PRI_PMMS_ADDR_WIDTH 14
/* Get the offset to be added to the chiplet base addr to get the unicast address */
#define PRI_PMMGS_OFFSET_MASK(addr) ((addr) & ((1 << PRI_PMMGS_ADDR_WIDTH) - 1))
#define PRI_PMMGS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMGS_ADDR_WIDTH) - 1)))
#define PRI_PMMGS_OFFSET_MASK(addr) ((addr) & (BIT32(PRI_PMMGS_ADDR_WIDTH) - 1U))
#define PRI_PMMGS_BASE_ADDR_MASK(addr) ((addr) & (~(BIT32(PRI_PMMGS_ADDR_WIDTH) - 1U)))
#define PRI_PMMS_ADDR_MASK(addr) ((addr) & ((1 << PRI_PMMS_ADDR_WIDTH) - 1))
#define PRI_PMMS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMS_ADDR_WIDTH) - 1)))
#define PRI_PMMS_ADDR_MASK(addr) ((addr) & (BIT32(PRI_PMMS_ADDR_WIDTH) - 1U))
#define PRI_PMMS_BASE_ADDR_MASK(addr) ((addr) & (~(BIT32(PRI_PMMS_ADDR_WIDTH) - 1U)))
#endif /* GR_PRI_GV11B_H */

18
drivers/gpu/nvgpu/include/nvgpu/pmu.h
View File

@@ -104,16 +104,14 @@
#define PMU_INVALID_SEQ_DESC (~0U)
enum {
GK20A_PMU_DMAIDX_UCODE = 0,
GK20A_PMU_DMAIDX_VIRT = 1,
GK20A_PMU_DMAIDX_PHYS_VID = 2,
GK20A_PMU_DMAIDX_PHYS_SYS_COH = 3,
GK20A_PMU_DMAIDX_PHYS_SYS_NCOH = 4,
GK20A_PMU_DMAIDX_RSVD = 5,
GK20A_PMU_DMAIDX_PELPG = 6,
GK20A_PMU_DMAIDX_END = 7
};
#define GK20A_PMU_DMAIDX_UCODE U32(0)
#define GK20A_PMU_DMAIDX_VIRT U32(1)
#define GK20A_PMU_DMAIDX_PHYS_VID U32(2)
#define GK20A_PMU_DMAIDX_PHYS_SYS_COH U32(3)
#define GK20A_PMU_DMAIDX_PHYS_SYS_NCOH U32(4)
#define GK20A_PMU_DMAIDX_RSVD U32(5)
#define GK20A_PMU_DMAIDX_PELPG U32(6)
#define GK20A_PMU_DMAIDX_END U32(7)
enum {
PMU_SEQ_STATE_FREE = 0,

2
drivers/gpu/nvgpu/pmgr/pwrdev.c
View File

@@ -111,7 +111,7 @@ static struct boardobj *construct_pwr_device(struct gk20a *g,
board_obj_ptr->pmudatainit = _pwr_domains_pmudatainit_ina3221;
pwrdev->super.power_rail = ina3221->super.power_rail;
pwrdev->super.i2c_dev_idx = ina3221->super.i2c_dev_idx;
pwrdev->super.power_corr_factor = (1 << 12);
pwrdev->super.power_corr_factor = BIT32(12);
pwrdev->super.bIs_inforom_config = false;
/* Set INA3221-specific information */

3
drivers/gpu/nvgpu/therm/thrmchannel.c
View File

@@ -70,6 +70,7 @@ static struct boardobj *construct_channel_device(struct gk20a *g,
struct therm_channel *pchannel;
struct therm_channel_device *pchannel_device;
int status;
u16 scale_shift = BIT16(8);
struct therm_channel_device *therm_device = (struct therm_channel_device*)pargs;
status = boardobj_construct_super(g, &board_obj_ptr,
@@ -86,7 +87,7 @@ static struct boardobj *construct_channel_device(struct gk20a *g,
g->ops.therm.get_internal_sensor_limits(&pchannel->temp_max,
&pchannel->temp_min);
pchannel->scaling = (1 << 8);
pchannel->scaling = S16(scale_shift);
pchannel->offset = 0;
pchannel_device->therm_dev_idx = therm_device->therm_dev_idx;