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gpu: nvgpu: Fix MISRA 12.2 misc bit shift errors

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MISRA rule 12.2 states that the right hand operand of a shift
operator shall lie in the range zero to one less than the width
in bits of the essential type of the left hand operand. This
patch will fix these violations by casting them to an appropriate
type or using the relevant BITxx() macros.

JIRA NVGPU-666

Change-Id: I57b6081e9bd98c45ca9f7aa5f35e1d2d66ed0134
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945655
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Srirangan Madhavan
2018-11-08 16:30:51 +05:30
committed by mobile promotions
parent 9c982aba65
commit 63d1b7113a
13 changed files with 51 additions and 40 deletions
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4
drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
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@@ -170,7 +170,7 @@ static inline unsigned int gk20a_ce_get_method_size(int request_operation,
shift = (MAX_CE_ALIGN(chunk) != 0ULL) ?
__ffs(MAX_CE_ALIGN(chunk)) : MAX_CE_SHIFT;
width = chunk >> shift;
height = 1 << shift;
height = BIT32(shift);
width = MAX_CE_ALIGN(width);
chunk -= (u64) height * width;
@@ -244,7 +244,7 @@ int gk20a_ce_prepare_submit(u64 src_buf,
shift = (MAX_CE_ALIGN(chunk) != 0ULL) ?
__ffs(MAX_CE_ALIGN(chunk)) : MAX_CE_SHIFT;
height = chunk >> shift;
width = 1 << shift;
width = BIT32(shift);
height = MAX_CE_ALIGN(height);
chunk_size = (u64) height * width;