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gpu: nvgpu: common: Fix MISRA 15.6 violations
This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/common/ JIRA NVGPU-989 Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1786207 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -194,8 +194,9 @@ int nvgpu_lockless_allocator_init(struct gk20a *g, struct nvgpu_allocator *__a,
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/* chain the elements together to form the initial free list */
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nr_nodes = (int)count;
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for (i = 0; i < nr_nodes; i++)
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for (i = 0; i < nr_nodes; i++) {
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a->next[i] = i + 1;
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}
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a->next[nr_nodes - 1] = -1;
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a->base = base;
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