gpu: nvgpu: vgpu: add mmu_debug_mode support

Added two new IVC commands that set gr and fb mmu debug mode.

Bug 2586624

Change-Id: I358fb04713a9754fb209c0a90d02130dd4a1caf6
Reviewed-on: https://git-master.nvidia.com/r/2204980
(cherry picked from commit db4e5b09891aff075dfffb7cc2fe0630a71ab9a6)
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288347
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -279,6 +279,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
 	vgpu/css_vgpu.o \
 	vgpu/ecc_vgpu.o \
 	vgpu/clk_vgpu.o \
+	vgpu/fb_vgpu.o \
 	vgpu/gm20b/vgpu_gr_gm20b.o \
 	vgpu/gp10b/vgpu_hal_gp10b.o  \
 	vgpu/gp10b/vgpu_gr_gp10b.o  \

drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h

@@ -123,6 +123,8 @@ enum {
 	TEGRA_VGPU_CMD_RESUME = 83,
 	TEGRA_VGPU_CMD_GET_ECC_INFO = 84,
 	TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85,
+	TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE = 88,
+	TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE = 89,
 };
 
 struct tegra_vgpu_connect_params {
@@ -617,6 +619,15 @@ struct tegra_vgpu_tsg_bind_channel_ex_params {
 	u32 runqueue_sel;
 };
 
+struct tegra_vgpu_fb_set_mmu_debug_mode_params {
+	u8 enable;
+};
+
+struct tegra_vgpu_gr_set_mmu_debug_mode_params {
+	u64 ch_handle;
+	u8 enable;
+};
+
 struct tegra_vgpu_cmd_msg {
 	u32 cmd;
 	int ret;
@@ -679,6 +690,8 @@ struct tegra_vgpu_cmd_msg {
 		struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling;
 		struct tegra_vgpu_ecc_info_params ecc_info;
 		struct tegra_vgpu_ecc_counter_params ecc_counter;
+		struct tegra_vgpu_fb_set_mmu_debug_mode_params fb_set_mmu_debug_mode;
+		struct tegra_vgpu_gr_set_mmu_debug_mode_params gr_set_mmu_debug_mode;
 		char padding[192];
 	} params;
 };

drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,6 +39,7 @@ struct vm_gk20a;
 struct nvgpu_gr_ctx;
 struct nvgpu_cpu_time_correlation_sample;
 struct vgpu_ecc_stat;
+struct channel_gk20a;
 
 struct vgpu_priv_data {
 	u64 virt_handle;
@@ -104,4 +105,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g);
 
 bool vgpu_is_reduced_bar1(struct gk20a *g);
 
+int vgpu_gr_set_mmu_debug_mode(struct gk20a *g,
+			struct channel_gk20a *ch, bool enable);
 #endif

drivers/gpu/nvgpu/vgpu/fb_vgpu.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/vgpu/tegra_vgpu.h>
+#include <nvgpu/vgpu/vgpu.h>
+
+#include "fb_vgpu.h"
+
+void vgpu_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
+{
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct tegra_vgpu_fb_set_mmu_debug_mode_params *p =
+				&msg.params.fb_set_mmu_debug_mode;
+	int err;
+
+	msg.cmd = TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE;
+	msg.handle = vgpu_get_handle(g);
+	p->enable = enable ? 1U : 0U;
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	err = err != 0 ? err : msg.ret;
+	if (err != 0) {
+		nvgpu_err(g,
+			"fb set mmu debug mode failed err %d", err);
+	}
+}

drivers/gpu/nvgpu/vgpu/fb_vgpu.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef FB_VGPU_H
+#define FB_VGPU_H
+
+void vgpu_fb_set_mmu_debug_mode(struct gk20a *g, bool enable);
+
+#endif

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -41,6 +41,7 @@
 #include "vgpu/dbg_vgpu.h"
 #include "vgpu/fecs_trace_vgpu.h"
 #include "vgpu/css_vgpu.h"
+#include "vgpu/fb_vgpu.h"
 #include "gp10b/gp10b.h"
 #include "gp10b/hal_gp10b.h"
 #include "vgpu/gm20b/vgpu_gr_gm20b.h"
@@ -250,7 +251,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.read_wpr_info = NULL,
 		.is_debug_mode_enabled = NULL,
 		.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
-		.set_mmu_debug_mode = NULL,
+		.set_mmu_debug_mode = vgpu_fb_set_mmu_debug_mode,
 		.tlb_invalidate = vgpu_mm_tlb_invalidate,
 	},
 	.clock_gating = {

drivers/gpu/nvgpu/vgpu/gr_vgpu.c

@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU Graphics
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1378,3 +1378,21 @@ int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable)
 
 	return err ? err : msg.ret;
 }
+
+int vgpu_gr_set_mmu_debug_mode(struct gk20a *g,
+		struct channel_gk20a *ch, bool enable)
+{
+	struct tegra_vgpu_cmd_msg msg = {};
+	struct tegra_vgpu_gr_set_mmu_debug_mode_params *p =
+					&msg.params.gr_set_mmu_debug_mode;
+	int err;
+
+	msg.cmd = TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE;
+	msg.handle = vgpu_get_handle(g);
+	p->ch_handle = ch->virt_ctx;
+	p->enable = enable ? 1U : 0U;
+	err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
+	WARN_ON(err || msg.ret);
+
+	return err ? err : msg.ret;
+}

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c

@@ -44,7 +44,7 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g)
 	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true);
 	__nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true);
 	__nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true);
-	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false);
+	__nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true);
 
 	return 0;
 }

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -49,6 +49,7 @@
 #include "vgpu/dbg_vgpu.h"
 #include "vgpu/fecs_trace_vgpu.h"
 #include "vgpu/css_vgpu.h"
+#include "vgpu/fb_vgpu.h"
 #include "vgpu/gm20b/vgpu_gr_gm20b.h"
 #include "vgpu/gp10b/vgpu_mm_gp10b.h"
 #include "vgpu/gp10b/vgpu_gr_gp10b.h"
@@ -189,7 +190,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.get_hw_accessor_stream_out_mode =
 			gr_gv100_get_hw_accessor_stream_out_mode,
 		.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
-		.set_mmu_debug_mode = NULL,
+		.set_mmu_debug_mode = vgpu_gr_set_mmu_debug_mode,
 		.record_sm_error_state = gv11b_gr_record_sm_error_state,
 		.clear_sm_error_state = vgpu_gr_clear_sm_error_state,
 		.suspend_contexts = vgpu_gr_suspend_contexts,
@@ -291,7 +292,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.read_wpr_info = NULL,
 		.is_debug_mode_enabled = NULL,
 		.set_debug_mode = vgpu_mm_mmu_set_debug_mode,
-		.set_mmu_debug_mode = NULL,
+		.set_mmu_debug_mode = vgpu_fb_set_mmu_debug_mode,
 		.tlb_invalidate = vgpu_mm_tlb_invalidate,
 		.hub_isr = gv11b_fb_hub_isr,
 		.enable_hub_intr = gv11b_fb_enable_hub_intr,