From 6434bc497558705f0d4162496f99762d7ea3b0db Mon Sep 17 00:00:00 2001
From: Philip Elcan <pelcan@nvidia.com>
Date: Tue, 6 Aug 2019 11:04:50 -0400
Subject: [PATCH] gpu: nvgpu: bus: fix CERT-C violations

INT31-C requires checking that data isn't misinterpreted after casting.
Fix these violations by using safe ops.

JIRA NVGPU-3868

Change-Id: I380ca9b6dae0f409fc3cb132e19715f5d1c03aac
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2170236
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/hal/bus/bus_gm20b_fusa.c | 4 +++-
 drivers/gpu/nvgpu/hal/bus/bus_gp10b_fusa.c | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/nvgpu/hal/bus/bus_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/bus/bus_gm20b_fusa.c
index 5a32d2b41..9a51a38c2 100644
--- a/drivers/gpu/nvgpu/hal/bus/bus_gm20b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/bus/bus_gm20b_fusa.c
@@ -27,6 +27,7 @@
 #include <nvgpu/enabled.h>
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/safe_ops.h>
 
 #include "bus_gm20b.h"
 
@@ -37,7 +38,8 @@ int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
 	struct nvgpu_timeout timeout;
 	int err = 0;
 	u64 iova = nvgpu_inst_block_addr(g, bar1_inst);
-	u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v());
+	u32 ptr_v = nvgpu_safe_cast_u64_to_u32(iova
+					>> bus_bar1_block_ptr_shift_v());
 
 	nvgpu_log_info(g, "bar1 inst block ptr: 0x%08x", ptr_v);
 
diff --git a/drivers/gpu/nvgpu/hal/bus/bus_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/bus/bus_gp10b_fusa.c
index b5a916a88..90f771a30 100644
--- a/drivers/gpu/nvgpu/hal/bus/bus_gp10b_fusa.c
+++ b/drivers/gpu/nvgpu/hal/bus/bus_gp10b_fusa.c
@@ -24,6 +24,7 @@
 #include <nvgpu/mm.h>
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
+#include <nvgpu/safe_ops.h>
 
 #include "bus_gp10b.h"
 
@@ -34,7 +35,8 @@ int gp10b_bus_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst)
 	struct nvgpu_timeout timeout;
 	int err = 0;
 	u64 iova = nvgpu_inst_block_addr(g, bar2_inst);
-	u32 ptr_v = (u32)(iova >> bus_bar2_block_ptr_shift_v());
+	u32 ptr_v = nvgpu_safe_cast_u64_to_u32(iova
+					>> bus_bar2_block_ptr_shift_v());
 
 	nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", ptr_v);