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gpu: nvgpu: move mapped regs to gk20a
- moved reg fields to gk20a - added os abstract register accessor in nvgpu/io.h - defined linux register access abstract implementation - hook up with posix. posix implementation of the register accessor uses the high 4 bit of address to identify register apertures then call the according callbacks. It helps to unify code across OSes. Bug 2999617 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Change-Id: Ifcb737e4b4d5b1d8bae310ae50b1ce0aa04f750c Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497937 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -12,125 +12,20 @@
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/types.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include "os_linux.h"
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static void nvgpu_warn_on_no_regs(void)
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u32 nvgpu_os_readl(uintptr_t addr)
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{
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WARN_ONCE(true, "Attempted access to GPU regs after unmapping!");
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return readl((void __iomem *)addr);
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}
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void nvgpu_writel(struct gk20a *g, u32 r, u32 v)
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void nvgpu_os_writel(u32 v, uintptr_t addr)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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writel_relaxed(v, l->regs + r);
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nvgpu_wmb();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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writel(v, (void __iomem *)addr);
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}
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void nvgpu_writel_relaxed(struct gk20a *g, u32 r, u32 v)
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void nvgpu_os_writel_relaxed(u32 v, uintptr_t addr)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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writel_relaxed(v, l->regs + r);
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}
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}
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u32 nvgpu_readl(struct gk20a *g, u32 r)
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{
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u32 v = nvgpu_readl_impl(g, r);
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if (v == 0xffffffff)
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nvgpu_check_gpu_state(g);
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return v;
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}
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u32 nvgpu_readl_impl(struct gk20a *g, u32 r)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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u32 v = 0xffffffff;
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if (unlikely(!l->regs)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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v = readl(l->regs + r);
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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return v;
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}
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void nvgpu_writel_loop(struct gk20a *g, u32 r, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->regs)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v);
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} else {
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nvgpu_wmb();
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do {
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writel_relaxed(v, l->regs + r);
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} while (readl(l->regs + r) != v);
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nvgpu_log(g, gpu_dbg_reg, "r=0x%x v=0x%x", r, v);
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}
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}
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void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (unlikely(!l->bar1)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
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} else {
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nvgpu_wmb();
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writel_relaxed(v, l->bar1 + b);
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
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}
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}
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u32 nvgpu_bar1_readl(struct gk20a *g, u32 b)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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u32 v = 0xffffffff;
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if (unlikely(!l->bar1)) {
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nvgpu_warn_on_no_regs();
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v);
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} else {
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v = readl(l->bar1 + b);
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nvgpu_log(g, gpu_dbg_reg, "b=0x%x v=0x%x", b, v);
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}
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return v;
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}
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bool nvgpu_io_exists(struct gk20a *g)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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return l->regs != NULL;
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}
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bool nvgpu_io_valid_reg(struct gk20a *g, u32 r)
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{
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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return r < resource_size(l->regs);
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writel_relaxed(v, (void __iomem *)addr);
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}
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