diff --git a/drivers/gpu/nvgpu/Makefile.shared.configs b/drivers/gpu/nvgpu/Makefile.shared.configs
index 308ebdd61..e46b5457c 100644
--- a/drivers/gpu/nvgpu/Makefile.shared.configs
+++ b/drivers/gpu/nvgpu/Makefile.shared.configs
@@ -47,7 +47,6 @@ NVGPU_COMMON_CFLAGS		:=
 
 NVGPU_COMMON_CFLAGS		+=		\
 	-DCONFIG_TEGRA_GK20A_NVHOST		\
-	-DCONFIG_GK20A_CYCLE_STATS		\
 	-DCONFIG_TEGRA_T19X_GRHOST		\
 	-DCONFIG_NVGPU_SUPPORT_TURING		\
 	-DCONFIG_TEGRA_GK20A_PMU=1		\
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index 4d5e8218c..7e44cfd88 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -177,11 +177,6 @@ srcs += common/utils/enabled.c \
 	hal/gr/falcon/gr_falcon_gm20b.c \
 	hal/gr/falcon/gr_falcon_gp10b.c \
 	hal/gr/falcon/gr_falcon_gv11b.c \
-	hal/gr/gr/gr_gk20a.c \
-	hal/gr/gr/gr_gm20b.c \
-	hal/gr/gr/gr_gp10b.c \
-	hal/gr/gr/gr_gv100.c \
-	hal/gr/gr/gr_gv11b.c \
 	hal/init/hal_gm20b.c \
 	hal/init/hal_gm20b_litter.c \
 	hal/init/hal_gp10b.c \
@@ -315,7 +310,13 @@ srcs += common/debugger.c \
 	hal/regops/regops_tu104.c \
 	hal/gr/hwpm_map/hwpm_map_gv100.c \
 	hal/perf/perf_gm20b.c \
-	hal/perf/perf_gv11b.c
+	hal/perf/perf_gv11b.c \
+	hal/gr/gr/gr_gk20a.c \
+	hal/gr/gr/gr_gm20b.c \
+	hal/gr/gr/gr_gp10b.c \
+	hal/gr/gr/gr_gv11b.c \
+	hal/gr/gr/gr_gv100.c \
+	hal/gr/gr/gr_tu104.c
 endif
 
 ifeq ($(NVGPU_FEATURE_CE),1)
@@ -497,7 +498,6 @@ srcs += common/sec2/sec2.c \
 	hal/gr/init/gr_init_gv100.c \
 	hal/gr/init/gr_init_tu104.c \
 	hal/gr/intr/gr_intr_tu104.c \
-	hal/gr/gr/gr_tu104.c \
 	hal/fbpa/fbpa_tu104.c \
 	hal/init/hal_tu104.c \
 	hal/init/hal_tu104_litter.c \
diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c
index 5ba373b45..f61698be3 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel.c
+++ b/drivers/gpu/nvgpu/common/fifo/channel.c
@@ -291,7 +291,9 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force)
 	struct dbg_session_data *session_data, *tmp_s;
 	struct dbg_session_channel_data *ch_data, *tmp;
 	int err;
+#ifdef NVGPU_DEBUGGER
 	bool deferred_reset_pending;
+#endif
 
 	nvgpu_log_fn(g, " ");
 
@@ -372,6 +374,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force)
 			__func__, "references");
 	}
 
+#ifdef NVGPU_DEBUGGER
 	/* if engine reset was deferred, perform it now */
 	nvgpu_mutex_acquire(&f->deferred_reset_mutex);
 	deferred_reset_pending = g->fifo.deferred_reset_pending;
@@ -386,6 +389,7 @@ static void gk20a_free_channel(struct nvgpu_channel *ch, bool force)
 
 		nvgpu_mutex_release(&g->fifo.engines_reset_mutex);
 	}
+#endif
 
 	if (!nvgpu_channel_as_bound(ch)) {
 		goto unbind;
@@ -2718,6 +2722,7 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g,
 	nvgpu_kfree(g, infos);
 }
 
+#ifdef NVGPU_DEBUGGER
 int nvgpu_channel_deferred_reset_engines(struct gk20a *g,
 		struct nvgpu_channel *ch)
 {
@@ -2782,3 +2787,4 @@ fail:
 
 	return err;
 }
+#endif
diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c
index 037a3f966..aeb914ab4 100644
--- a/drivers/gpu/nvgpu/common/fifo/engines.c
+++ b/drivers/gpu/nvgpu/common/fifo/engines.c
@@ -563,6 +563,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 				nvgpu_err(g, "failed to halt gr pipe");
 			}
 
+#ifdef NVGPU_DEBUGGER
 			/*
 			 * resetting engine using mc_enable_r() is not
 			 * enough, we do full init sequence
@@ -573,6 +574,7 @@ void nvgpu_engine_reset(struct gk20a *g, u32 engine_id)
 			if (err != 0) {
 				nvgpu_err(g, "failed to reset gr engine");
 			}
+#endif
 		} else {
 			nvgpu_log(g, gpu_dbg_info,
 				"HALT gr pipe not supported and "
@@ -922,6 +924,7 @@ u32 nvgpu_engine_get_runlist_busy_engines(struct gk20a *g, u32 runlist_id)
 	return eng_bitmask;
 }
 
+#ifdef NVGPU_DEBUGGER
 bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id,
 		u32 engine_subid, bool fake_fault)
 {
@@ -962,6 +965,7 @@ bool nvgpu_engine_should_defer_reset(struct gk20a *g, u32 engine_id,
 
 	return g->ops.engine.is_fault_engine_subid_gpc(g, engine_subid);
 }
+#endif
 
 u32 nvgpu_engine_mmu_fault_id_to_veid(struct gk20a *g, u32 mmu_fault_id,
 			u32 gr_eng_fault_id)
diff --git a/drivers/gpu/nvgpu/common/fifo/fifo.c b/drivers/gpu/nvgpu/common/fifo/fifo.c
index 98d1680c4..a0c3f64bd 100644
--- a/drivers/gpu/nvgpu/common/fifo/fifo.c
+++ b/drivers/gpu/nvgpu/common/fifo/fifo.c
@@ -48,8 +48,10 @@ void nvgpu_fifo_cleanup_sw_common(struct gk20a *g)
 	nvgpu_engine_cleanup_sw(g);
 	nvgpu_pbdma_cleanup_sw(g);
 
+#ifdef NVGPU_DEBUGGER
 	f->deferred_reset_pending = false;
 	nvgpu_mutex_destroy(&f->deferred_reset_mutex);
+#endif
 	nvgpu_mutex_destroy(&f->engines_reset_mutex);
 	nvgpu_mutex_destroy(&f->intr.isr.mutex);
 }
@@ -78,7 +80,9 @@ int nvgpu_fifo_setup_sw_common(struct gk20a *g)
 
 	nvgpu_mutex_init(&f->intr.isr.mutex);
 	nvgpu_mutex_init(&f->engines_reset_mutex);
+#ifdef NVGPU_DEBUGGER
 	nvgpu_mutex_init(&f->deferred_reset_mutex);
+#endif
 
 	err = nvgpu_channel_setup_sw(g);
 	if (err != 0) {
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index 2007567ac..e4070c26f 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -215,6 +215,7 @@ int nvgpu_tsg_unbind_channel_common(struct nvgpu_tsg *tsg,
 	g->ops.channel.disable(ch);
 	nvgpu_rwsem_up_write(&tsg->ch_list_lock);
 
+#ifdef NVGPU_DEBUGGER
 	if (ch->mmu_debug_mode_enabled) {
 		err = nvgpu_tsg_set_mmu_debug_mode(tsg, ch, false);
 		if (err != 0) {
@@ -222,6 +223,7 @@ int nvgpu_tsg_unbind_channel_common(struct nvgpu_tsg *tsg,
 				ch->chid);
 		}
 	}
+#endif
 
 	/*
 	 * Don't re-enable all channels if TSG has timed out already
@@ -879,6 +881,7 @@ void nvgpu_tsg_reset_faulted_eng_pbdma(struct gk20a *g, struct nvgpu_tsg *tsg,
 	nvgpu_rwsem_up_read(&tsg->ch_list_lock);
 }
 
+#ifdef NVGPU_DEBUGGER
 int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg,
 		struct nvgpu_channel *ch, bool enable)
 {
@@ -924,3 +927,4 @@ int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg,
 
 	return err;
 }
+#endif
diff --git a/drivers/gpu/nvgpu/common/init/nvgpu_init.c b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
index 20a51ff8f..63a89dd28 100644
--- a/drivers/gpu/nvgpu/common/init/nvgpu_init.c
+++ b/drivers/gpu/nvgpu/common/init/nvgpu_init.c
@@ -350,11 +350,13 @@ int gk20a_finalize_poweron(struct gk20a *g)
 
 	nvgpu_mutex_acquire(&g->tpc_pg_lock);
 
+#ifdef NVGPU_DEBUGGER
 	if (g->can_tpc_powergate) {
 		if (g->ops.gr.powergate_tpc != NULL) {
 			g->ops.gr.powergate_tpc(g);
 		}
 	}
+#endif
 
 	/* prepare portion of sw required for enable hw */
 	err = nvgpu_gr_prepare_sw(g);
diff --git a/drivers/gpu/nvgpu/common/rc/rc.c b/drivers/gpu/nvgpu/common/rc/rc.c
index cfa10010b..36a3cba64 100644
--- a/drivers/gpu/nvgpu/common/rc/rc.c
+++ b/drivers/gpu/nvgpu/common/rc/rc.c
@@ -172,7 +172,7 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg,
 			 bool debug_dump, u32 rc_type)
 {
 	u32 eng_bitmask = 0U;
-	int err;
+	int err = 0;
 
 	nvgpu_mutex_acquire(&g->dbg_sessions_lock);
 
@@ -194,7 +194,9 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg,
 	 * changing until engine status is checked to make sure tsg
 	 * being recovered is not loaded on the engines
 	 */
+#ifdef NVGPU_DEBUGGER
 	err = g->ops.gr.disable_ctxsw(g);
+#endif
 
 	if (err != 0) {
 		/* if failed to disable ctxsw, just abort tsg */
@@ -204,6 +206,7 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg,
 		eng_bitmask = g->ops.engine.get_mask_on_id(g,
 				tsg->tsgid, true);
 
+#ifdef NVGPU_DEBUGGER
 		/*
 		 * it is ok to enable ctxsw before tsg is recovered. If engines
 		 * is 0, no engine recovery is needed and if it is  non zero,
@@ -215,6 +218,7 @@ void nvgpu_rc_tsg_and_related_engines(struct gk20a *g, struct nvgpu_tsg *tsg,
 		if (err != 0) {
 			nvgpu_err(g, "failed to enable ctxsw");
 		}
+#endif
 	}
 	nvgpu_log_info(g, "release engines_reset_mutex");
 	nvgpu_mutex_release(&g->fifo.engines_reset_mutex);
diff --git a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
index 130e07ded..5d9d7ff59 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -133,6 +133,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.get_num_pce = vgpu_ce_get_num_pce,
 	},
 	.gr = {
+#ifdef NVGPU_DEBUGGER
 		.set_alpha_circular_buffer_size = NULL,
 		.set_circular_buffer_size = NULL,
 		.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
@@ -179,6 +180,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.reset = NULL,
 		.disable_ctxsw = nvgpu_gr_disable_ctxsw,
 		.enable_ctxsw = nvgpu_gr_enable_ctxsw,
+#endif
 		.ctxsw_prog = {
 			.hw_get_fecs_header_size =
 				gm20b_ctxsw_prog_hw_get_fecs_header_size,
diff --git a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
index edf968a43..4354f0a30 100644
--- a/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -160,6 +160,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.get_num_pce = vgpu_ce_get_num_pce,
 	},
 	.gr = {
+#ifdef NVGPU_DEBUGGER
 		.set_alpha_circular_buffer_size = NULL,
 		.set_circular_buffer_size = NULL,
 		.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs,
@@ -213,6 +214,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.reset = NULL,
 		.disable_ctxsw = nvgpu_gr_disable_ctxsw,
 		.enable_ctxsw = nvgpu_gr_enable_ctxsw,
+#endif
 		.ctxsw_prog = {
 			.hw_get_fecs_header_size =
 				gm20b_ctxsw_prog_hw_get_fecs_header_size,
diff --git a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
index 42654e411..c7b364223 100644
--- a/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/fb/fb_gm20b.c
@@ -347,5 +347,7 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
 			fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
 	gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
 
+#ifdef NVGPU_DEBUGGER
 	g->ops.gr.set_debug_mode(g, enable);
+#endif
 }
diff --git a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c
index a3241eda9..063ef25e4 100644
--- a/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c
+++ b/drivers/gpu/nvgpu/hal/fifo/mmu_fault_gk20a.c
@@ -241,7 +241,6 @@ bool gk20a_fifo_handle_mmu_fault_locked(
 	bool debug_dump = true;
 	struct nvgpu_engine_status_info engine_status;
 	bool deferred_reset_pending = false;
-	struct nvgpu_fifo *f = &g->fifo;
 
 	nvgpu_log_fn(g, " ");
 
@@ -259,9 +258,11 @@ bool gk20a_fifo_handle_mmu_fault_locked(
 		fault_id = nvgpu_readl(g, fifo_intr_mmu_fault_id_r());
 		fake_fault = false;
 	}
-	nvgpu_mutex_acquire(&f->deferred_reset_mutex);
+#ifdef NVGPU_DEBUGGER
+	nvgpu_mutex_acquire(&g->fifo.deferred_reset_mutex);
 	g->fifo.deferred_reset_pending = false;
-	nvgpu_mutex_release(&f->deferred_reset_mutex);
+	nvgpu_mutex_release(&g->fifo.deferred_reset_mutex);
+#endif
 
 	/* go through all faulted engines */
 	for_each_set_bit(engine_mmu_fault_id, &fault_id, 32U) {
@@ -289,8 +290,10 @@ bool gk20a_fifo_handle_mmu_fault_locked(
 
 		if (ctxsw) {
 			g->ops.gr.falcon.dump_stats(g);
+#ifdef NVGPU_DEBUGGER
 			nvgpu_err(g, "  gr_status_r: 0x%x",
 				  g->ops.gr.get_gr_status(g));
+#endif
 		}
 
 		/* get the channel/TSG */
@@ -337,6 +340,7 @@ bool gk20a_fifo_handle_mmu_fault_locked(
 
 		/* check if engine reset should be deferred */
 		if (engine_id != NVGPU_INVALID_ENG_ID) {
+#ifdef NVGPU_DEBUGGER
 			bool defer = nvgpu_engine_should_defer_reset(g,
 					engine_id, mmfault_info.client_type,
 					fake_fault);
@@ -344,9 +348,9 @@ bool gk20a_fifo_handle_mmu_fault_locked(
 				g->fifo.deferred_fault_engines |= BIT(engine_id);
 
 				/* handled during channel free */
-				nvgpu_mutex_acquire(&f->deferred_reset_mutex);
+				nvgpu_mutex_acquire(&g->fifo.deferred_reset_mutex);
 				g->fifo.deferred_reset_pending = true;
-				nvgpu_mutex_release(&f->deferred_reset_mutex);
+				nvgpu_mutex_release(&g->fifo.deferred_reset_mutex);
 
 				deferred_reset_pending = true;
 
@@ -354,8 +358,11 @@ bool gk20a_fifo_handle_mmu_fault_locked(
 					   "sm debugger attached,"
 					   " deferring channel recovery to channel free");
 			} else {
+#endif
 				nvgpu_engine_reset(g, engine_id);
+#ifdef NVGPU_DEBUGGER
 			}
+#endif
 		}
 
 #ifdef CONFIG_GK20A_CTXSW_TRACE
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
index 4daf23bf6..f50ae5f53 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
@@ -64,6 +64,7 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 		goto fail;
 	}
 
+#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS)
 	if (class_num == MAXWELL_B) {
 		switch (offset << 2) {
 		case NVB197_SET_SHADER_EXCEPTIONS:
@@ -83,6 +84,7 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			break;
 		}
 	}
+#endif
 
 fail:
 	return ret;
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
index 9b4978c2f..d3ba83962 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
@@ -219,6 +219,7 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 		goto fail;
 	}
 
+#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS)
 	if (class_num == PASCAL_A) {
 		switch (offset << 2) {
 		case NVC097_SET_SHADER_EXCEPTIONS:
@@ -250,6 +251,7 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			break;
 		}
 	}
+#endif
 
 fail:
 	return ret;
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
index 93dafc9be..8660e3f4d 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
@@ -199,6 +199,7 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 		goto fail;
 	}
 
+#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS)
 	if (class_num == VOLTA_A) {
 		switch (offset << 2) {
 		case NVC397_SET_SHADER_EXCEPTIONS:
@@ -236,6 +237,7 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			break;
 		}
 	}
+#endif
 
 fail:
 	return ret;
diff --git a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
index e4caa53d4..8d711ddd3 100644
--- a/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
+++ b/drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
@@ -91,6 +91,7 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 		goto fail;
 	}
 
+#if defined(NVGPU_DEBUGGER) && defined(NVGPU_GRAPHICS)
 	if (class_num == TURING_A) {
 		switch (offset << 2) {
 		case NVC597_SET_SHADER_EXCEPTIONS:
@@ -131,6 +132,7 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
 			break;
 		}
 	}
+#endif
 
 fail:
 	return ret;
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
index e072e9d8e..98c72dcfe 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gm20b.c
@@ -150,6 +150,7 @@ static const struct gpu_ops gm20b_ops = {
 		.isr_nonstall = gk20a_ce2_nonstall_isr,
 	},
 	.gr = {
+#ifdef NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
 			gr_gm20b_set_alpha_circular_buffer_size,
@@ -195,6 +196,7 @@ static const struct gpu_ops gm20b_ops = {
 		.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
 		.disable_ctxsw = nvgpu_gr_disable_ctxsw,
 		.enable_ctxsw = nvgpu_gr_enable_ctxsw,
+#endif /* NVGPU_DEBUGGER */
 		.ctxsw_prog = {
 			.hw_get_fecs_header_size =
 				gm20b_ctxsw_prog_hw_get_fecs_header_size,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
index 6f5d12c1e..3f3b81fd5 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gp10b.c
@@ -179,6 +179,7 @@ static const struct gpu_ops gp10b_ops = {
 		.isr_nonstall = gp10b_ce_nonstall_isr,
 	},
 	.gr = {
+#ifdef NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
 			gr_gp10b_set_alpha_circular_buffer_size,
@@ -229,6 +230,7 @@ static const struct gpu_ops gp10b_ops = {
 		.esr_bpt_pending_events = gm20b_gr_esr_bpt_pending_events,
 		.disable_ctxsw = nvgpu_gr_disable_ctxsw,
 		.enable_ctxsw = nvgpu_gr_enable_ctxsw,
+#endif /* NVGPU_DEBUGGER */
 		.ecc = {
 			.detect = gp10b_ecc_detect_enabled_units,
 			.init = gp10b_ecc_init,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
index ba5229955..07b0d977f 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_gv11b.c
@@ -220,6 +220,7 @@ static const struct gpu_ops gv11b_ops = {
 				gv11b_ce_mthd_buffer_fault_in_bar2_fault,
 	},
 	.gr = {
+#ifdef NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
 			gr_gv11b_set_alpha_circular_buffer_size,
@@ -282,6 +283,7 @@ static const struct gpu_ops gv11b_ops = {
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
 		.disable_ctxsw = nvgpu_gr_disable_ctxsw,
 		.enable_ctxsw = nvgpu_gr_enable_ctxsw,
+#endif /* NVGPU_DEBUGGER */
 		.ecc = {
 			.detect = gv11b_ecc_detect_enabled_units,
 			.init = gv11b_ecc_init,
diff --git a/drivers/gpu/nvgpu/hal/init/hal_tu104.c b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
index 6acc10bd9..05e8480d3 100644
--- a/drivers/gpu/nvgpu/hal/init/hal_tu104.c
+++ b/drivers/gpu/nvgpu/hal/init/hal_tu104.c
@@ -264,6 +264,7 @@ static const struct gpu_ops tu104_ops = {
 				gv11b_ce_mthd_buffer_fault_in_bar2_fault,
 	},
 	.gr = {
+#ifdef NVGPU_DEBUGGER
 		.get_gr_status = gr_gm20b_get_gr_status,
 		.set_alpha_circular_buffer_size =
 			gr_gv11b_set_alpha_circular_buffer_size,
@@ -325,6 +326,7 @@ static const struct gpu_ops tu104_ops = {
 		.esr_bpt_pending_events = gv11b_gr_esr_bpt_pending_events,
 		.disable_ctxsw = nvgpu_gr_disable_ctxsw,
 		.enable_ctxsw = nvgpu_gr_enable_ctxsw,
+#endif /* NVGPU_DEBUGGER */
 		.ecc = {
 			.detect = NULL,
 			.init = tu104_ecc_init,
diff --git a/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c b/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c
index 72e4b6954..5274e70f0 100644
--- a/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c
+++ b/drivers/gpu/nvgpu/hal/rc/rc_gv11b.c
@@ -95,7 +95,9 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g,
 #ifdef CONFIG_GK20A_CTXSW_TRACE
 			nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg);
 #endif
+#ifdef NVGPU_DEBUGGER
 			if (!g->fifo.deferred_reset_pending) {
+#endif
 				if (rc_type == RC_TYPE_MMU_FAULT) {
 					nvgpu_tsg_set_ctx_mmu_error(g, tsg);
 					/*
@@ -104,7 +106,9 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g,
 					 */
 					(void) nvgpu_tsg_mark_error(g, tsg);
 				}
+#ifdef NVGPU_DEBUGGER
 			}
+#endif
 
 			/*
 			 * remove all entries from this runlist; don't wait for
@@ -145,9 +149,11 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
 	u32 pbdma_bitmask = 0U;
 	struct nvgpu_runlist_info *runlist = NULL;
 	u32 engine_id;
-	u32 client_type = ~U32(0U);
 	struct nvgpu_fifo *f = &g->fifo;
+#ifdef NVGPU_DEBUGGER
+	u32 client_type = ~U32(0U);
 	bool deferred_reset_pending = false;
+#endif
 
 	nvgpu_log_info(g, "acquire engines_reset_mutex");
 	nvgpu_mutex_acquire(&f->engines_reset_mutex);
@@ -191,7 +197,9 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
 
 	if (rc_type == RC_TYPE_MMU_FAULT) {
 		gk20a_debug_dump(g);
+#ifdef NVGPU_DEBUGGER
 		client_type = mmufault->client_type;
+#endif
 		nvgpu_tsg_reset_faulted_eng_pbdma(g, tsg, true, true);
 	}
 
@@ -217,9 +225,11 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
 		nvgpu_preempt_poll_tsg_on_pbdma(g, tsg);
 	}
 
+#ifdef NVGPU_DEBUGGER
 	nvgpu_mutex_acquire(&f->deferred_reset_mutex);
 	g->fifo.deferred_reset_pending = false;
 	nvgpu_mutex_release(&f->deferred_reset_mutex);
+#endif
 
 	/* check if engine reset should be deferred */
 	for (i = 0U; i < f->num_runlists; i++) {
@@ -236,6 +246,7 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
 
 			engine_id = U32(bit);
 
+#ifdef NVGPU_DEBUGGER
 			if ((tsg != NULL) && nvgpu_engine_should_defer_reset(g,
 					engine_id, client_type, false)) {
 
@@ -252,8 +263,11 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
 					"sm debugger attached, deferring "
 					"channel recovery to channel free");
 			} else {
+#endif
 				nvgpu_engine_reset(g, engine_id);
+#ifdef NVGPU_DEBUGGER
 			}
+#endif
 		}
 	}
 
@@ -262,15 +276,19 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
 		nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg);
 #endif
 	if (tsg != NULL) {
+#ifdef NVGPU_DEBUGGER
 		if (deferred_reset_pending) {
 			g->ops.tsg.disable(tsg);
 		} else {
+#endif
 			if (rc_type == RC_TYPE_MMU_FAULT) {
 				nvgpu_tsg_set_ctx_mmu_error(g, tsg);
 			}
 			(void)nvgpu_tsg_mark_error(g, tsg);
 			nvgpu_tsg_abort(g, tsg, false);
+#ifdef NVGPU_DEBUGGER
 		}
+#endif
 	} else {
 		gv11b_fifo_locked_abort_runlist_active_tsgs(g, rc_type,
 			runlists_mask);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h
index 1c86e1a5a..d32dd1ad3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h
@@ -382,7 +382,9 @@ struct nvgpu_channel {
 	bool has_os_fence_framework_support;
 
 	bool is_privileged_channel;
+#ifdef NVGPU_DEBUGGER
 	bool mmu_debug_mode_enabled;
+#endif
 };
 static inline struct nvgpu_channel *
 nvgpu_channel_from_free_chs(struct nvgpu_list_node *node)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fifo.h b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
index cae73edfb..23ce2539f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fifo.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fifo.h
@@ -119,9 +119,11 @@ struct nvgpu_fifo {
 
 	} intr;
 
+#ifdef NVGPU_DEBUGGER
 	unsigned long deferred_fault_engines;
 	bool deferred_reset_pending;
 	struct nvgpu_mutex deferred_reset_mutex;
+#endif
 
 	u32 max_subctx_count;
 	u32 channel_base;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index cbc59d752..6066c28e4 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -262,6 +262,7 @@ struct gpu_ops {
 		void (*mthd_buffer_fault_in_bar2_fault)(struct gk20a *g);
 	} ce;
 	struct {
+#ifdef NVGPU_DEBUGGER
 		u32 (*get_gr_status)(struct gk20a *g);
 		void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset);
 		void (*set_alpha_circular_buffer_size)(struct gk20a *g,
@@ -389,6 +390,8 @@ struct gpu_ops {
 					enum nvgpu_event_id_type bpt_event);
 		int (*disable_ctxsw)(struct gk20a *g);
 		int (*enable_ctxsw)(struct gk20a *g);
+#endif
+
 		struct {
 			void (*detect)(struct gk20a *g);
 			int (*init)(struct gk20a *g);
@@ -403,6 +406,7 @@ struct gpu_ops {
 			struct nvgpu_hw_err_inject_info_desc * (*get_fecs_err_desc)
 				(struct gk20a *g);
 		} ecc;
+
 		struct {
 			u32 (*hw_get_fecs_header_size)(void);
 			u32 (*hw_get_gpccs_header_size)(void);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h
index 3eb66f9ad..b92bdb9b9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h
@@ -175,6 +175,8 @@ void nvgpu_tsg_set_ctxsw_timeout_accumulated_ms(struct nvgpu_tsg *tsg, u32 ms);
 void nvgpu_tsg_abort(struct gk20a *g, struct nvgpu_tsg *tsg, bool preempt);
 void nvgpu_tsg_reset_faulted_eng_pbdma(struct gk20a *g, struct nvgpu_tsg *tsg,
 		bool eng, bool pbdma);
+#ifdef NVGPU_DEBUGGER
 int nvgpu_tsg_set_mmu_debug_mode(struct nvgpu_tsg *tsg,
 		struct nvgpu_channel *ch, bool enable);
+#endif
 #endif /* NVGPU_TSG_H */