From 64e22ee54ba126c3fd4554a34e8777f76da4966d Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 25 Jan 2023 10:01:53 -0800 Subject: [PATCH] gpu: nvgpu: vgpu: add rleng_id to constants rl_eng_id is used to construct ram_fc_target_w. VF creates inst_block and ramfc on client side. Jira GVSCI-15769 Change-Id: Id641e644e829bfaf6a3bb0bb758c142f0a514db3 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863431 Tested-by: mobile promotions Reviewed-by: mobile promotions --- drivers/gpu/nvgpu/common/vgpu/top/top_vgpu.c | 3 ++- drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/vgpu/top/top_vgpu.c b/drivers/gpu/nvgpu/common/vgpu/top/top_vgpu.c index 82d4ad311..8c1a9b1b8 100644 --- a/drivers/gpu/nvgpu/common/vgpu/top/top_vgpu.c +++ b/drivers/gpu/nvgpu/common/vgpu/top/top_vgpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -59,6 +59,7 @@ struct nvgpu_device *vgpu_top_parse_next_dev(struct gk20a *g, u32 *token) dev->intr_id = nvgpu_ffs(engines->info[*token].intr_mask) - 1; dev->reset_id = nvgpu_ffs(engines->info[*token].reset_mask) - 1; dev->runlist_id = engines->info[*token].runlist_id; + dev->rleng_id = engines->info[*token].rleng_id; dev->pbdma_id = engines->info[*token].pbdma_id; dev->inst_id = engines->info[*token].inst_id; dev->pri_base = engines->info[*token].pri_base; diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 2ad4d8d82..ae200c50a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h @@ -1,7 +1,7 @@ /* * Tegra GPU Virtualization Interfaces to Server * - * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -448,6 +448,7 @@ struct tegra_vgpu_engines_info { u32 intr_mask; u32 reset_mask; u32 runlist_id; + u32 rleng_id; u32 pbdma_id; u32 inst_id; u32 pri_base;