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gpu: nvgpu: Add RISCV LS PMU support
-Add RISCV LS PMU support by adding RISCV LS PMU ucode to the blob. -Modify the PMU RTOS sequence based on NEXT CORE enable flag. JIRA NVGPU-6303 Change-Id: I4e2b989f9903b72a6327c931eb3c02f8cef2aa75 Signed-off-by: mkumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447388 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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mkumbar
@@ -102,6 +102,44 @@ int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img)
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exit:
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return err;
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}
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#if defined(CONFIG_NVGPU_NEXT)
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s32 nvgpu_acr_lsf_pmu_ncore_ucode_details(struct gk20a *g, void *lsf_ucode_img)
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{
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struct lsf_ucode_desc *lsf_desc;
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struct nvgpu_firmware *fw_sig;
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struct nvgpu_firmware *fw_desc;
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struct nvgpu_firmware *fw_image;
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struct flcn_ucode_img *p_img =
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(struct flcn_ucode_img *)lsf_ucode_img;
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s32 err = 0;
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lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
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if (lsf_desc == NULL) {
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err = -ENOMEM;
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goto exit;
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}
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fw_sig = nvgpu_pmu_fw_sig_desc(g, g->pmu);
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fw_desc = nvgpu_pmu_fw_desc_desc(g, g->pmu);
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fw_image = nvgpu_pmu_fw_image_desc(g, g->pmu);
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nvgpu_memcpy((u8 *)lsf_desc, (u8 *)fw_sig->data,
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min_t(size_t, sizeof(*lsf_desc), fw_sig->size));
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lsf_desc->falcon_id = FALCON_ID_PMU_NEXT_CORE;
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p_img->ndesc = (struct falcon_next_core_ucode_desc *)(void *)fw_desc->data;
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p_img->data = (u32 *)(void *)fw_image->data;
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p_img->data_size = U32(fw_image->size);
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p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
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p_img->is_next_core_img = true;
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exit:
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return err;
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}
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#endif
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#endif
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int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
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@@ -431,51 +469,60 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
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sizeof(struct lsf_ucode_desc));
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}
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pnode->lsb_header.ucode_size = pnode->ucode_img.data_size;
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if (!pnode->ucode_img.is_next_core_img) {
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pnode->lsb_header.ucode_size = pnode->ucode_img.data_size;
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/* Uses a loader. that is has a desc */
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pnode->lsb_header.data_size = LSB_HDR_DATA_SIZE;
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/* Uses a loader. that is has a desc */
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pnode->lsb_header.data_size = LSB_HDR_DATA_SIZE;
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/*
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* The loader code size is already aligned (padded) such that
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* the code following it is aligned, but the size in the image
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* desc is not, bloat it up to be on a 256 byte alignment.
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*/
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pnode->lsb_header.bl_code_size = ALIGN(
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pnode->ucode_img.desc->bootloader_size,
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LSF_BL_CODE_SIZE_ALIGNMENT);
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full_app_size = nvgpu_safe_add_u32(
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ALIGN(pnode->ucode_img.desc->app_size,
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LSF_BL_CODE_SIZE_ALIGNMENT),
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pnode->lsb_header.bl_code_size);
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pnode->lsb_header.ucode_size = nvgpu_safe_add_u32(ALIGN(
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pnode->ucode_img.desc->app_resident_data_offset,
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LSF_BL_CODE_SIZE_ALIGNMENT),
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/*
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* The loader code size is already aligned (padded) such that
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* the code following it is aligned, but the size in the image
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* desc is not, bloat it up to be on a 256 byte alignment.
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*/
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pnode->lsb_header.bl_code_size = ALIGN(
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pnode->ucode_img.desc->bootloader_size,
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LSF_BL_CODE_SIZE_ALIGNMENT);
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full_app_size = nvgpu_safe_add_u32(
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ALIGN(pnode->ucode_img.desc->app_size,
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LSF_BL_CODE_SIZE_ALIGNMENT),
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pnode->lsb_header.bl_code_size);
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pnode->lsb_header.data_size = nvgpu_safe_sub_u32(full_app_size,
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pnode->lsb_header.ucode_size);
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/*
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* Though the BL is located at 0th offset of the image, the VA
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* is different to make sure that it doesn't collide the actual OS
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* VA range
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*/
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pnode->lsb_header.bl_imem_off =
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pnode->ucode_img.desc->bootloader_imem_offset;
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pnode->lsb_header.ucode_size = nvgpu_safe_add_u32(ALIGN(
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pnode->ucode_img.desc->app_resident_data_offset,
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LSF_BL_CODE_SIZE_ALIGNMENT),
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pnode->lsb_header.bl_code_size);
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pnode->lsb_header.flags = NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE;
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pnode->lsb_header.data_size = nvgpu_safe_sub_u32(full_app_size,
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pnode->lsb_header.ucode_size);
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/*
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* Though the BL is located at 0th offset of the image, the VA
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* is different to make sure that it doesn't collide the actual OS
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* VA range
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*/
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pnode->lsb_header.bl_imem_off =
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pnode->ucode_img.desc->bootloader_imem_offset;
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if (falcon_id == FALCON_ID_PMU) {
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data = NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE;
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pnode->lsb_header.flags = data;
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pnode->lsb_header.flags = NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE;
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if (falcon_id == FALCON_ID_PMU) {
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data = NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE;
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pnode->lsb_header.flags = data;
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}
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if (g->acr->lsf[falcon_id].is_priv_load) {
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pnode->lsb_header.flags |=
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NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE;
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}
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} else {
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pnode->lsb_header.ucode_size = 0;
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pnode->lsb_header.data_size = 0;
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pnode->lsb_header.bl_code_size = 0;
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pnode->lsb_header.bl_imem_off = 0;
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pnode->lsb_header.bl_data_size = 0;
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pnode->lsb_header.bl_data_off = 0;
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}
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if (g->acr->lsf[falcon_id].is_priv_load) {
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pnode->lsb_header.flags |=
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NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE;
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}
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}
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/* Adds a ucode image to the list of managed ucode images managed. */
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@@ -710,7 +757,8 @@ static int lsf_gen_wpr_requirements(struct gk20a *g,
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/* Finally, update ucode surface size to include updates */
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pnode->full_ucode_size = wpr_offset -
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pnode->lsb_header.ucode_off;
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if (pnode->wpr_header.falcon_id != FALCON_ID_PMU) {
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if (pnode->wpr_header.falcon_id != FALCON_ID_PMU &&
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pnode->wpr_header.falcon_id != FALCON_ID_PMU_NEXT_CORE) {
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pnode->lsb_header.app_code_off =
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pnode->lsb_header.bl_code_size;
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pnode->lsb_header.app_code_size =
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@@ -721,6 +769,7 @@ static int lsf_gen_wpr_requirements(struct gk20a *g,
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pnode->lsb_header.app_data_size =
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pnode->lsb_header.data_size;
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}
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pnode = pnode->next;
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}
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@@ -942,22 +991,25 @@ static int lsfm_init_wpr_contents(struct gk20a *g,
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nvgpu_acr_dbg(g, "flags :%x",
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pnode->lsb_header.flags);
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/*
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* If this falcon has a boot loader and related args,
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* flush them.
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*/
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/* Populate gen bl and flush to memory */
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err = lsfm_fill_flcn_bl_gen_desc(g, pnode);
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if (err != 0) {
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nvgpu_err(g, "bl_gen_desc failed err=%d", err);
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return err;
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if (!pnode->ucode_img.is_next_core_img) {
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/*
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* If this falcon has a boot loader and related args,
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* flush them.
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*/
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/* Populate gen bl and flush to memory */
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err = lsfm_fill_flcn_bl_gen_desc(g, pnode);
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if (err != 0) {
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nvgpu_err(g, "bl_gen_desc failed err=%d", err);
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return err;
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}
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nvgpu_mem_wr_n(g, ucode, pnode->lsb_header.bl_data_off,
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&pnode->bl_gen_desc, pnode->bl_gen_desc_size);
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}
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nvgpu_mem_wr_n(g, ucode, pnode->lsb_header.bl_data_off,
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&pnode->bl_gen_desc, pnode->bl_gen_desc_size);
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/* Copying of ucode */
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nvgpu_mem_wr_n(g, ucode, pnode->lsb_header.ucode_off,
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pnode->ucode_img.data, pnode->ucode_img.data_size);
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pnode = pnode->next;
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i = nvgpu_safe_add_u32(i, 1U);
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}
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