gpu: nvgpu: unit: fifo: move assert to unit_assert

unit_assert macro is provided to check a condition and execute bail_out
action given as a second argument.
Currently, in fifo unit, unit_assert() is redefined as assert with
common bail_out action. However, name assert() creates confusion with
linux assert macro. So, this patch removes redefined assert macro and
replaces with unit_assert.

Jira NVGPU-4684

Change-Id: I3a880f965a191f16efdabced5e23723e66ecaf3c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2276863
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

userspace/units/fifo/engine/gm20b/nvgpu-engine-gm20b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -53,8 +53,6 @@
 	} while (0)
 #endif
 
-#define assert(cond)	unit_assert(cond, goto done)
-
 #define branches_str test_fifo_flags_str
 #define pruned	test_fifo_subtest_pruned
 
@@ -91,12 +89,13 @@ int test_gm20b_read_engine_status_info(struct unit_module *m,
 	};
 	char *ctxsw_status_label = NULL;
 
-	assert(f->num_engines > 0);
-	assert(f->engine_info[0].engine_enum == NVGPU_ENGINE_GR);
+	unit_assert(f->num_engines > 0, goto done);
+	unit_assert(f->engine_info[0].engine_enum == NVGPU_ENGINE_GR,
+		goto done);
 
 	nvgpu_writel(g, fifo_engine_status_r(engine_id), 0xbeef);
 	gm20b_read_engine_status_info(g, NVGPU_INVALID_ENG_ID, &status);
-	assert(status.reg_data == 0);
+	unit_assert(status.reg_data == 0, goto done);
 
 	for (branches = 0; branches < F_ENGINE_READ_STATUS_LAST; branches++) {
 
@@ -201,14 +200,22 @@ int test_gm20b_read_engine_status_info(struct unit_module *m,
 
 			gm20b_read_engine_status_info(g, engine_id, &status);
 
-			assert(status.is_busy == expected.is_busy);
-			assert(status.is_faulted == expected.is_faulted);
-			assert(status.ctxsw_in_progress == expected.ctxsw_in_progress);
-			assert(status.ctxsw_status == expected.ctxsw_status);
-			assert(status.ctx_id == expected.ctx_id);
-			assert(status.ctx_id_type == expected.ctx_id_type);
-			assert(status.ctx_next_id == expected.ctx_next_id);
-			assert(status.ctx_next_id_type == expected.ctx_next_id_type);
+			unit_assert(status.is_busy == expected.is_busy,
+					goto done);
+			unit_assert(status.is_faulted == expected.is_faulted,
+					goto done);
+			unit_assert(status.ctxsw_in_progress ==
+					expected.ctxsw_in_progress, goto done);
+			unit_assert(status.ctxsw_status ==
+					expected.ctxsw_status, goto done);
+			unit_assert(status.ctx_id ==
+					expected.ctx_id, goto done);
+			unit_assert(status.ctx_id_type ==
+					expected.ctx_id_type, goto done);
+			unit_assert(status.ctx_next_id ==
+					expected.ctx_next_id, goto done);
+			unit_assert(status.ctx_next_id_type ==
+					expected.ctx_next_id_type, goto done);
 		}
 	}
 	ret = UNIT_SUCCESS;

userspace/units/fifo/engine/gp10b/nvgpu-engine-gp10b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -55,8 +55,6 @@
 	} while (0)
 #endif
 
-#define assert(cond)	unit_assert(cond, goto done)
-
 #define branches_str test_fifo_flags_str
 #define pruned test_fifo_subtest_pruned
 
@@ -198,8 +196,9 @@ int test_gp10b_engine_init_ce_info(struct unit_module *m,
 	u.m = m;
 	u.gops = g->ops;
 
-	assert(f->num_engines > 0);
-	assert(f->engine_info[0].engine_enum == NVGPU_ENGINE_GR);
+	unit_assert(f->num_engines > 0, goto done);
+	unit_assert(f->engine_info[0].engine_enum == NVGPU_ENGINE_GR,
+			goto done);
 
 	g->ops.top.get_device_info = wrap_top_get_device_info;
 	g->ops.pbdma.find_for_runlist = wrap_pbdma_find_for_runlist;
@@ -237,11 +236,11 @@ int test_gp10b_engine_init_ce_info(struct unit_module *m,
 		}
 
 		if (branches & fail) {
-			assert(err != 0);
-			assert(f->num_engines < (1 + num_lce));
+			unit_assert(err != 0, goto done);
+			unit_assert(f->num_engines < (1 + num_lce), goto done);
 		} else {
-			assert(err == 0);
-			assert(f->num_engines = (1 + num_lce));
+			unit_assert(err == 0, goto done);
+			unit_assert(f->num_engines = (1 + num_lce), goto done);
 		}
 	}
 

userspace/units/fifo/engine/gv100/nvgpu-engine-gv100.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -54,8 +54,6 @@
 	} while (0)
 #endif
 
-#define assert(cond)	unit_assert(cond, goto done)
-
 #define branches_str test_fifo_flags_str
 #define pruned test_fifo_subtest_pruned
 
@@ -78,11 +76,11 @@ int test_gv100_read_engine_status_info(struct unit_module *m,
 
 	nvgpu_writel(g, fifo_engine_status_r(engine_id), 0);
 	gv100_read_engine_status_info(g, engine_id, &status);
-	assert(status.in_reload_status == false);
+	unit_assert(status.in_reload_status == false, goto done);
 
 	nvgpu_writel(g, fifo_engine_status_r(engine_id), BIT(29));
 	gv100_read_engine_status_info(g, engine_id, &status);
-	assert(status.in_reload_status == true);
+	unit_assert(status.in_reload_status == true, goto done);
 
 	ret = UNIT_SUCCESS;
 done:
@@ -156,12 +154,12 @@ int test_gv100_dump_engine_status(struct unit_module *m,
 
 	unit_ctx.engine_id = 0;
 	gv100_dump_engine_status(g, &o);
-	assert(unit_ctx.engine_id == (num_engines - 1));
+	unit_assert(unit_ctx.engine_id == (num_engines - 1), goto done);
 
 	unit_ctx.engine_id = (u32)~0;
 	g->ops.get_litter_value = stub_get_litter_value_0;
 	gv100_dump_engine_status(g, &o);
-	assert(unit_ctx.engine_id == (u32)~0);
+	unit_assert(unit_ctx.engine_id == (u32)~0, goto done);
 
 	ret = UNIT_SUCCESS;
 done:

userspace/units/fifo/engine/gv11b/nvgpu-engine-gv11b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -52,18 +52,16 @@
 	} while (0)
 #endif
 
-#define assert(cond)	unit_assert(cond, goto done)
-
 int test_gv11b_is_fault_engine_subid_gpc(struct unit_module *m,
 		struct gk20a *g, void *args)
 {
 
 	int ret = UNIT_FAIL;
 
-	assert(gv11b_is_fault_engine_subid_gpc(g,
-		gmmu_fault_client_type_gpc_v()) == true);
-	assert(gv11b_is_fault_engine_subid_gpc(g,
-		gmmu_fault_client_type_hub_v()) == false);
+	unit_assert(gv11b_is_fault_engine_subid_gpc(g,
+		gmmu_fault_client_type_gpc_v()) == true, goto done);
+	unit_assert(gv11b_is_fault_engine_subid_gpc(g,
+		gmmu_fault_client_type_hub_v()) == false, goto done);
 
 	ret = UNIT_SUCCESS;
 done:

userspace/units/fifo/engine/nvgpu-engine.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -72,8 +72,6 @@ static void subtest_setup(u32 branches)
 #define subtest_pruned	test_fifo_subtest_pruned
 #define branches_str	test_fifo_flags_str
 
-#define assert(cond)	unit_assert(cond, goto done)
-
 #define F_ENGINE_SETUP_SW_ENGINE_INFO_ENOMEM	BIT(0)
 #define F_ENGINE_SETUP_SW_ENGINE_LIST_ENOMEM	BIT(1)
 #define F_ENGINE_SETUP_SW_INIT_INFO_FAIL	BIT(2)
@@ -110,7 +108,7 @@ int test_engine_setup_sw(struct unit_module *m,
 	u32 prune = fail;
 
 	err = test_fifo_setup_gv11b_reg_space(m, g);
-	assert(err == 0);
+	unit_assert(err == 0, goto done);
 
 	gv11b_init_hal(g);
 
@@ -144,13 +142,13 @@ int test_engine_setup_sw(struct unit_module *m,
 		err = nvgpu_engine_setup_sw(g);
 
 		if (branches & fail) {
-			assert(err != 0);
-			assert(f->active_engines_list == NULL);
-			assert(f->engine_info == NULL);
+			unit_assert(err != 0, goto done);
+			unit_assert(f->active_engines_list == NULL, goto done);
+			unit_assert(f->engine_info == NULL, goto done);
 		} else {
-			assert(err == 0);
-			assert(f->active_engines_list != NULL);
-			assert(f->engine_info != NULL);
+			unit_assert(err == 0, goto done);
+			unit_assert(f->active_engines_list != NULL, goto done);
+			unit_assert(f->engine_info != NULL, goto done);
 			nvgpu_engine_cleanup_sw(g);
 		}
 	}
@@ -245,10 +243,10 @@ int test_engine_init_info(struct unit_module *m,
 		err = nvgpu_engine_init_info(f);
 
 		if (branches & fail) {
-			assert(err != 0);
+			unit_assert(err != 0, goto done);
 		} else {
-			assert(err == 0);
-			assert(f->num_engines > 0);
+			unit_assert(err == 0, goto done);
+			unit_assert(f->num_engines > 0, goto done);
 		}
 	}
 
@@ -277,18 +275,21 @@ int test_engine_ids(struct unit_module *m,
 	unit_ctx.ce_mask = 0;
 	unit_ctx.eng_mask = 0;
 
-	assert(nvgpu_engine_check_valid_id(g, U32_MAX) == false);
+	unit_assert(nvgpu_engine_check_valid_id(g, U32_MAX) == false,
+				goto done);
 
-	assert(nvgpu_engine_get_ids(g, &engine_id, 1, NVGPU_ENGINE_INVAL) == 0);
+	unit_assert(nvgpu_engine_get_ids(g, &engine_id, 1,
+				NVGPU_ENGINE_INVAL) == 0, goto done);
 
 	for (e = NVGPU_ENGINE_GR; e < NVGPU_ENGINE_INVAL; e++) {
 
 		n = nvgpu_engine_get_ids(g, engine_ids, MAX_ENGINE_IDS, e);
-		assert(n > 0);
+		unit_assert(n > 0, goto done);
 		for (i = 0; i < n; i++) {
 			engine_id = engine_ids[i];
 
-			assert(nvgpu_engine_check_valid_id(g, engine_id) == true);
+			unit_assert(nvgpu_engine_check_valid_id(g, engine_id) ==
+							true, goto done);
 			unit_ctx.eng_mask |= BIT(engine_id);
 			if (e == NVGPU_ENGINE_ASYNC_CE || e == NVGPU_ENGINE_GRCE) {
 				unit_ctx.ce_mask |= BIT(engine_id);
@@ -296,10 +297,11 @@ int test_engine_ids(struct unit_module *m,
 		}
 	}
 
-	assert(nvgpu_engine_get_ids(g, &engine_id, 1, NVGPU_ENGINE_GR) == 1);
-	assert(engine_id == nvgpu_engine_get_gr_id(g));
-	assert(unit_ctx.eng_mask != 0);
-	assert(unit_ctx.ce_mask != 0);
+	unit_assert(nvgpu_engine_get_ids(g, &engine_id, 1,
+					NVGPU_ENGINE_GR) == 1, goto done);
+	unit_assert(engine_id == nvgpu_engine_get_gr_id(g), goto done);
+	unit_assert(unit_ctx.eng_mask != 0, goto done);
+	unit_assert(unit_ctx.ce_mask != 0, goto done);
 
 	ret = UNIT_SUCCESS;
 done:
@@ -320,16 +322,16 @@ int test_engine_get_active_eng_info(struct unit_module *m,
 		unit_verbose(m, "engine_id=%u\n", engine_id);
 		info = nvgpu_engine_get_active_eng_info(g, engine_id);
 		if (nvgpu_engine_check_valid_id(g, engine_id)) {
-			assert(info != NULL);
-			assert(info->engine_id == engine_id);
+			unit_assert(info != NULL, goto done);
+			unit_assert(info->engine_id == engine_id, goto done);
 			eng_mask |= BIT(engine_id);
 		} else {
-			assert(info == NULL);
+			unit_assert(info == NULL, goto done);
 		}
 	}
 	unit_verbose(m, "eng_mask=%x\n", eng_mask);
 	unit_verbose(m, "unit_ctx.eng_mask=%x\n", unit_ctx.eng_mask);
-	assert(eng_mask == unit_ctx.eng_mask);
+	unit_assert(eng_mask == unit_ctx.eng_mask, goto done);
 
 	ret = UNIT_SUCCESS;
 done:
@@ -344,14 +346,14 @@ int test_engine_enum_from_type(struct unit_module *m,
 
 	engine_enum = nvgpu_engine_enum_from_type(g,
 		top_device_info_type_enum_graphics_v());
-	assert(engine_enum == NVGPU_ENGINE_GR);
+	unit_assert(engine_enum == NVGPU_ENGINE_GR, goto done);
 
 	engine_enum = nvgpu_engine_enum_from_type(g,
 		top_device_info_type_enum_lce_v());
-	assert(engine_enum == NVGPU_ENGINE_ASYNC_CE);
+	unit_assert(engine_enum == NVGPU_ENGINE_ASYNC_CE, goto done);
 
 	engine_enum = nvgpu_engine_enum_from_type(g, 0xff);
-	assert(engine_enum == NVGPU_ENGINE_INVAL);
+	unit_assert(engine_enum == NVGPU_ENGINE_INVAL, goto done);
 
 	ret = UNIT_SUCCESS;
 done:
@@ -371,22 +373,22 @@ int test_engine_interrupt_mask(struct unit_module *m,
 	u32 engine_id;
 	struct nvgpu_fifo *f = &g->fifo;
 
-	assert(intr_mask != 0U);
+	unit_assert(intr_mask != 0U, goto done);
 	for (engine_id = 0; engine_id < f->max_engines; engine_id++) {
 		unit_verbose(m, "engine_id=%u\n", engine_id);
 		mask = nvgpu_engine_act_interrupt_mask(g, engine_id);
 		if (nvgpu_engine_check_valid_id(g, engine_id)) {
-			assert(mask != 0);
-			assert((mask & intr_mask) == mask);
+			unit_assert(mask != 0, goto done);
+			unit_assert((mask & intr_mask) == mask, goto done);
 			all_mask |= mask;
 		} else {
-			assert(mask == 0);
+			unit_assert(mask == 0, goto done);
 		}
 	}
-	assert(intr_mask == all_mask);
+	unit_assert(intr_mask == all_mask, goto done);
 
 	ce_reset_mask = nvgpu_engine_get_all_ce_reset_mask(g);
-	assert(ce_reset_mask != 0);;
+	unit_assert(ce_reset_mask != 0, goto done);;
 
 	ret = UNIT_SUCCESS;
 done: