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gpu: nvgpu: fix misra rule 17.7 & 5.6 violations in falcon unit

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nvgpu_timer_init return value was not used in falcon functions. fix it.
flcn_status keyword was used variable names as well as typedefs. Make
typedef name different.

JIRA NVGPU-3271

Change-Id: I6899b752f9d04f1f55cc6b2954e13716076697b1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108546
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-04-29 12:19:22 +05:30
committed by mobile promotions
parent 3766cc3672
commit 6583783174
10 changed files with 39 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
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@@ -112,7 +112,7 @@ struct pmu_hdr {
#define PMU_CMD_HDR_SIZE U32(sizeof(struct pmu_hdr))
#define nv_pmu_hdr pmu_hdr
typedef u8 flcn_status;
typedef u8 falcon_status;
#define PMU_DMEM_ALLOC_ALIGNMENT 32U
#define PMU_DMEM_ALIGNMENT 4U

2
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/boardobj.h
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@@ -111,7 +111,7 @@ struct nv_pmu_boardobj_cmd {
struct nv_pmu_boardobj_msg_grp {
u8 msg_type;
bool b_success;
flcn_status flcn_status;
falcon_status flcn_status;
u8 class_id;
};

2
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/clk.h
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@@ -586,7 +586,7 @@ struct nv_pmu_clk_rpc {
u8 function;
bool b_supported;
bool b_success;
flcn_status flcn_status;
falcon_status flcn_status;
union {
struct nv_pmu_clk_vf_change_inject clk_vf_change_inject;
struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1;

3
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/cmn.h
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@@ -23,6 +23,7 @@
#define NVGPU_PMUIF_CMN_H
#include <nvgpu/types.h>
#include <nvgpu/flcnif_cmn.h>
/*
* Defines the logical queue IDs that must be used when submitting
@@ -100,7 +101,7 @@ struct nv_pmu_rpc_header {
/* RPC call flags (@see PMU_RPC_FLAGS) */
u8 flags;
/* Falcon's status code to describe failures*/
u8 flcn_status;
falcon_status flcn_status;
/* RPC's total exec. time (measured on nvgpu driver side)*/
u32 exec_time_nv_ns;
/* RPC's actual exec. time (measured on PMU side)*/

2
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h
View File

@@ -112,7 +112,7 @@ struct nv_pmu_perf_rpc {
u8 function;
bool b_supported;
bool b_success;
flcn_status flcn_status;
falcon_status flcn_status;
union {
struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval;
struct nv_pmu_perf_rpc_vfe_load vfe_load;

6
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pmgr.h
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@@ -412,21 +412,21 @@ struct nv_pmu_pmgr_cmd {
struct nv_pmu_pmgr_msg_set_object {
u8 msg_type;
bool b_success;
flcn_status flcnstatus;
falcon_status flcnstatus;
u8 object_type;
};
struct nv_pmu_pmgr_msg_query {
u8 msg_type;
bool b_success;
flcn_status flcnstatus;
falcon_status flcnstatus;
u8 cmd_type;
};
struct nv_pmu_pmgr_msg_load {
u8 msg_type;
bool b_success;
flcn_status flcnstatus;
falcon_status flcnstatus;
};
struct nv_pmu_pmgr_msg_unload {

2
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/pmu.h
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@@ -116,7 +116,7 @@ struct pmu_init_msg_pmu_v4 {
struct pmu_init_msg_pmu_v5 {
u8 msg_type;
u8 flcn_status;
falcon_status flcn_status;
u8 queue_index[PMU_QUEUE_COUNT_FOR_V5];
u16 queue_size[PMU_QUEUE_COUNT_FOR_V5];
u16 queue_offset;

4
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/therm.h
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@@ -37,12 +37,12 @@
struct nv_pmu_therm_rpc_slct_event_temp_th_set {
s32 temp_threshold;
u8 event_id;
flcn_status flcn_stat;
falcon_status flcn_stat;
};
struct nv_pmu_therm_rpc_slct {
u32 mask_enabled;
flcn_status flcn_stat;
falcon_status flcn_stat;
};
struct nv_pmu_therm_rpc {

2
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/volt.h
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@@ -284,7 +284,7 @@ struct nv_pmu_volt_rpc {
u8 function;
bool b_supported;
bool b_success;
flcn_status flcn_status;
falcon_status flcn_status;
union {
struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data;
struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage;