gpu: nvgpu: Allow disabling CDE functionality

CDE is a Tegra SoC specific feature. Add new config option
CONFIG_NVGPU_SUPPORT_CDE and #ifdef all CDE specific code with it.

JIRA NVGPU-4

Change-Id: I6f0b0047d6ba2b5c36c2eb9b8a1514776741f5b5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648002
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-01-24 12:42:57 -08:00
committed by mobile promotions
parent b6ab47d396
commit 662c441467
12 changed files with 79 additions and 29 deletions

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@@ -128,3 +128,10 @@ config GK20A_VIDMEM
Enable support for using and allocating buffers in a distinct video Enable support for using and allocating buffers in a distinct video
memory aperture (in contrast to general system memory), available on memory aperture (in contrast to general system memory), available on
GPUs that have their own banks. PCIe GPUs have this, for example. GPUs that have their own banks. PCIe GPUs have this, for example.
config NVGPU_SUPPORT_CDE
bool "Support extraction of comptags for CDE"
depends on GK20A
default y
help
Enable support for extraction of comptags for CDE.

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@@ -38,12 +38,9 @@ nvgpu-y := \
common/linux/vm.o \ common/linux/vm.o \
common/linux/intr.o \ common/linux/intr.o \
common/linux/sysfs.o \ common/linux/sysfs.o \
common/linux/cde.o \
common/linux/io.o \ common/linux/io.o \
common/linux/io_usermode.o \ common/linux/io_usermode.o \
common/linux/rwsem.o \ common/linux/rwsem.o \
common/linux/cde_gm20b.o \
common/linux/cde_gp10b.o \
common/linux/comptags.o \ common/linux/comptags.o \
common/linux/dmabuf.o \ common/linux/dmabuf.o \
common/linux/sched.o \ common/linux/sched.o \
@@ -132,7 +129,6 @@ nvgpu-$(CONFIG_DEBUG_FS) += \
common/linux/debug.o \ common/linux/debug.o \
common/linux/debug_gr.o \ common/linux/debug_gr.o \
common/linux/debug_fifo.o \ common/linux/debug_fifo.o \
common/linux/debug_cde.o \
common/linux/debug_ce.o \ common/linux/debug_ce.o \
common/linux/debug_pmu.o \ common/linux/debug_pmu.o \
common/linux/debug_sched.o \ common/linux/debug_sched.o \
@@ -301,3 +297,13 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
common/linux/vgpu/gv11b/vgpu_fifo_gv11b.o \ common/linux/vgpu/gv11b/vgpu_fifo_gv11b.o \
common/linux/vgpu/gv11b/vgpu_subctx_gv11b.o \ common/linux/vgpu/gv11b/vgpu_subctx_gv11b.o \
common/linux/vgpu/gv11b/vgpu_tsg_gv11b.o common/linux/vgpu/gv11b/vgpu_tsg_gv11b.o
nvgpu-$(CONFIG_NVGPU_SUPPORT_CDE) += \
common/linux/cde.o \
common/linux/cde_gm20b.o \
common/linux/cde_gp10b.o
ifeq ($(CONFIG_DEBUG_FS),y)
nvgpu-$(CONFIG_NVGPU_SUPPORT_CDE) += \
common/linux/debug_cde.o
endif

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@@ -44,6 +44,8 @@
#include "os_linux.h" #include "os_linux.h"
#include "dmabuf.h" #include "dmabuf.h"
#include "channel.h" #include "channel.h"
#include "cde_gm20b.h"
#include "cde_gp10b.h"
#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h> #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
@@ -1749,3 +1751,24 @@ int gk20a_mark_compressible_write(struct gk20a *g, u32 buffer_fd,
dma_buf_put(dmabuf); dma_buf_put(dmabuf);
return 0; return 0;
} }
int nvgpu_cde_init_ops(struct nvgpu_os_linux *l)
{
struct gk20a *g = &l->g;
u32 ver = g->params.gpu_arch + g->params.gpu_impl;
switch (ver) {
case GK20A_GPUID_GM20B:
case GK20A_GPUID_GM20B_B:
l->ops.cde = gm20b_cde_ops.cde;
break;
case NVGPU_GPUID_GP10B:
l->ops.cde = gp10b_cde_ops.cde;
break;
default:
/* CDE is optional, so today ignoring unknown chip is fine */
break;
}
return 0;
}

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@@ -321,5 +321,6 @@ int gk20a_prepare_compressible_read(
int gk20a_mark_compressible_write( int gk20a_mark_compressible_write(
struct gk20a *g, u32 buffer_fd, u32 valid_compbits, u64 offset, struct gk20a *g, u32 buffer_fd, u32 valid_compbits, u64 offset,
u32 zbc_color); u32 zbc_color);
int nvgpu_cde_init_ops(struct nvgpu_os_linux *l);
#endif #endif

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@@ -1,5 +1,5 @@
/* /*
* Copyright (C) 2017 NVIDIA Corporation. All rights reserved. * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
* *
* This software is licensed under the terms of the GNU General Public * This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and * License version 2, as published by the Free Software Foundation, and
@@ -377,7 +377,9 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
gr_gk20a_debugfs_init(g); gr_gk20a_debugfs_init(g);
gk20a_pmu_debugfs_init(g); gk20a_pmu_debugfs_init(g);
gk20a_railgating_debugfs_init(g); gk20a_railgating_debugfs_init(g);
#ifdef CONFIG_NVGPU_SUPPORT_CDE
gk20a_cde_debugfs_init(g); gk20a_cde_debugfs_init(g);
#endif
gk20a_ce_debugfs_init(g); gk20a_ce_debugfs_init(g);
nvgpu_alloc_debugfs_init(g); nvgpu_alloc_debugfs_init(g);
nvgpu_hal_debugfs_init(g); nvgpu_hal_debugfs_init(g);

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@@ -148,7 +148,9 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
g->aggressive_sync_destroy = platform->aggressive_sync_destroy; g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh; g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
g->has_syncpoints = platform->has_syncpoints; g->has_syncpoints = platform->has_syncpoints;
#ifdef CONFIG_NVGPU_SUPPORT_CDE
g->has_cde = platform->has_cde; g->has_cde = platform->has_cde;
#endif
g->ptimer_src_freq = platform->ptimer_src_freq; g->ptimer_src_freq = platform->ptimer_src_freq;
g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g)); g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g));
g->can_railgate = platform->can_railgate_init; g->can_railgate = platform->can_railgate_init;

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@@ -333,10 +333,12 @@ static int gk20a_ctrl_prepare_compressible_read(
struct gk20a *g, struct gk20a *g,
struct nvgpu_gpu_prepare_compressible_read_args *args) struct nvgpu_gpu_prepare_compressible_read_args *args)
{ {
int ret = -ENOSYS;
#ifdef CONFIG_NVGPU_SUPPORT_CDE
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
struct nvgpu_fence fence; struct nvgpu_fence fence;
struct gk20a_fence *fence_out = NULL; struct gk20a_fence *fence_out = NULL;
int ret = 0;
int flags = args->submit_flags; int flags = args->submit_flags;
fence.id = args->fence.syncpt_id; fence.id = args->fence.syncpt_id;
@@ -377,18 +379,21 @@ static int gk20a_ctrl_prepare_compressible_read(
} }
} }
gk20a_fence_put(fence_out); gk20a_fence_put(fence_out);
#endif
return 0; return ret;
} }
static int gk20a_ctrl_mark_compressible_write( static int gk20a_ctrl_mark_compressible_write(
struct gk20a *g, struct gk20a *g,
struct nvgpu_gpu_mark_compressible_write_args *args) struct nvgpu_gpu_mark_compressible_write_args *args)
{ {
int ret; int ret = -ENOSYS;
#ifdef CONFIG_NVGPU_SUPPORT_CDE
ret = gk20a_mark_compressible_write(g, args->handle, ret = gk20a_mark_compressible_write(g, args->handle,
args->valid_compbits, args->offset, args->zbc_color); args->valid_compbits, args->offset, args->zbc_color);
#endif
return ret; return ret;
} }

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@@ -48,17 +48,18 @@
#include "module.h" #include "module.h"
#include "module_usermode.h" #include "module_usermode.h"
#include "intr.h" #include "intr.h"
#include "cde.h"
#include "ioctl.h" #include "ioctl.h"
#include "sim.h" #include "sim.h"
#include "os_linux.h" #include "os_linux.h"
#include "cde_gm20b.h"
#include "cde_gp10b.h"
#include "ctxsw_trace.h" #include "ctxsw_trace.h"
#include "driver_common.h" #include "driver_common.h"
#include "channel.h" #include "channel.h"
#ifdef CONFIG_NVGPU_SUPPORT_CDE
#include "cde.h"
#endif
#define CLASS_NAME "nvidia-gpu" #define CLASS_NAME "nvidia-gpu"
/* TODO: Change to e.g. "nvidia-gpu%s" once we have symlinks in place. */ /* TODO: Change to e.g. "nvidia-gpu%s" once we have symlinks in place. */
@@ -180,23 +181,13 @@ static int gk20a_restore_registers(struct gk20a *g)
static int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l) static int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
{ {
struct gk20a *g = &l->g; int err = 0;
u32 ver = g->params.gpu_arch + g->params.gpu_impl;
switch (ver) { #ifdef CONFIG_NVGPU_SUPPORT_CDE
case GK20A_GPUID_GM20B: err = nvgpu_cde_init_ops(l);
case GK20A_GPUID_GM20B_B: #endif
l->ops.cde = gm20b_cde_ops.cde;
break;
case NVGPU_GPUID_GP10B:
l->ops.cde = gp10b_cde_ops.cde;
break;
default:
/* CDE is optional, so today ignoring unknown chip is fine */
break;
}
return 0; return err;
} }
int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l) int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l)
@@ -285,8 +276,10 @@ int gk20a_pm_finalize_poweron(struct device *dev)
gk20a_scale_resume(dev_from_gk20a(g)); gk20a_scale_resume(dev_from_gk20a(g));
#ifdef CONFIG_NVGPU_SUPPORT_CDE
if (platform->has_cde) if (platform->has_cde)
gk20a_init_cde_support(l); gk20a_init_cde_support(l);
#endif
err = gk20a_sched_ctrl_init(g); err = gk20a_sched_ctrl_init(g);
if (err) { if (err) {
@@ -325,7 +318,9 @@ static int gk20a_lockout_registers(struct gk20a *g)
static int gk20a_pm_prepare_poweroff(struct device *dev) static int gk20a_pm_prepare_poweroff(struct device *dev)
{ {
struct gk20a *g = get_gk20a(dev); struct gk20a *g = get_gk20a(dev);
#ifdef CONFIG_NVGPU_SUPPORT_CDE
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
#endif
int ret = 0; int ret = 0;
struct gk20a_platform *platform = gk20a_get_platform(dev); struct gk20a_platform *platform = gk20a_get_platform(dev);
bool irqs_enabled; bool irqs_enabled;
@@ -348,7 +343,9 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
gk20a_scale_suspend(dev); gk20a_scale_suspend(dev);
#ifdef CONFIG_NVGPU_SUPPORT_CDE
gk20a_cde_suspend(l); gk20a_cde_suspend(l);
#endif
ret = gk20a_prepare_poweroff(g); ret = gk20a_prepare_poweroff(g);
if (ret) if (ret)
@@ -1239,7 +1236,9 @@ return_err:
int nvgpu_remove(struct device *dev, struct class *class) int nvgpu_remove(struct device *dev, struct class *class)
{ {
struct gk20a *g = get_gk20a(dev); struct gk20a *g = get_gk20a(dev);
#ifdef CONFIG_NVGPU_SUPPORT_CDE
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
#endif
struct gk20a_platform *platform = gk20a_get_platform(dev); struct gk20a_platform *platform = gk20a_get_platform(dev);
int err; int err;
@@ -1251,8 +1250,10 @@ int nvgpu_remove(struct device *dev, struct class *class)
if (nvgpu_mem_is_valid(&g->syncpt_mem)) if (nvgpu_mem_is_valid(&g->syncpt_mem))
nvgpu_dma_free(g, &g->syncpt_mem); nvgpu_dma_free(g, &g->syncpt_mem);
#ifdef CONFIG_NVGPU_SUPPORT_CDE
if (platform->has_cde) if (platform->has_cde)
gk20a_cde_destroy(l); gk20a_cde_destroy(l);
#endif
#ifdef CONFIG_GK20A_CTXSW_TRACE #ifdef CONFIG_GK20A_CTXSW_TRACE
gk20a_ctxsw_trace_cleanup(g); gk20a_ctxsw_trace_cleanup(g);

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@@ -217,7 +217,9 @@ struct gk20a_platform {
/* source frequency for ptimer in hz */ /* source frequency for ptimer in hz */
u32 ptimer_src_freq; u32 ptimer_src_freq;
#ifdef CONFIG_NVGPU_SUPPORT_CDE
bool has_cde; bool has_cde;
#endif
/* soc name for finding firmware files */ /* soc name for finding firmware files */
const char *soc_name; const char *soc_name;

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@@ -948,7 +948,9 @@ struct gk20a_platform gm20b_tegra_platform = {
.dump_platform_dependencies = gk20a_tegra_debug_dump, .dump_platform_dependencies = gk20a_tegra_debug_dump,
#ifdef CONFIG_NVGPU_SUPPORT_CDE
.has_cde = true, .has_cde = true,
#endif
.soc_name = "tegra21x", .soc_name = "tegra21x",

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@@ -409,7 +409,9 @@ struct gk20a_platform gp10b_tegra_platform = {
.dump_platform_dependencies = gk20a_tegra_debug_dump, .dump_platform_dependencies = gk20a_tegra_debug_dump,
#ifdef CONFIG_NVGPU_SUPPORT_CDE
.has_cde = true, .has_cde = true,
#endif
.clk_round_rate = gp10b_round_clk_rate, .clk_round_rate = gp10b_round_clk_rate,
.get_clk_freqs = gp10b_clk_get_freqs, .get_clk_freqs = gp10b_clk_get_freqs,

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@@ -211,9 +211,6 @@ static int gv11b_tegra_suspend(struct device *dev)
struct gk20a_platform gv11b_tegra_platform = { struct gk20a_platform gv11b_tegra_platform = {
.has_syncpoints = true, .has_syncpoints = true,
/* no cde. use sysmem compression */
.has_cde = false,
/* ptimer src frequency in hz*/ /* ptimer src frequency in hz*/
.ptimer_src_freq = 31250000, .ptimer_src_freq = 31250000,