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gpu: nvgpu: Allow disabling CDE functionality
CDE is a Tegra SoC specific feature. Add new config option CONFIG_NVGPU_SUPPORT_CDE and #ifdef all CDE specific code with it. JIRA NVGPU-4 Change-Id: I6f0b0047d6ba2b5c36c2eb9b8a1514776741f5b5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1648002 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -128,3 +128,10 @@ config GK20A_VIDMEM
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Enable support for using and allocating buffers in a distinct video
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memory aperture (in contrast to general system memory), available on
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GPUs that have their own banks. PCIe GPUs have this, for example.
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config NVGPU_SUPPORT_CDE
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bool "Support extraction of comptags for CDE"
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depends on GK20A
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default y
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help
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Enable support for extraction of comptags for CDE.
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@@ -38,12 +38,9 @@ nvgpu-y := \
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common/linux/vm.o \
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common/linux/intr.o \
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common/linux/sysfs.o \
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common/linux/cde.o \
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common/linux/io.o \
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common/linux/io_usermode.o \
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common/linux/rwsem.o \
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common/linux/cde_gm20b.o \
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common/linux/cde_gp10b.o \
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common/linux/comptags.o \
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common/linux/dmabuf.o \
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common/linux/sched.o \
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@@ -132,7 +129,6 @@ nvgpu-$(CONFIG_DEBUG_FS) += \
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common/linux/debug.o \
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common/linux/debug_gr.o \
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common/linux/debug_fifo.o \
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common/linux/debug_cde.o \
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common/linux/debug_ce.o \
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common/linux/debug_pmu.o \
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common/linux/debug_sched.o \
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@@ -301,3 +297,13 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
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common/linux/vgpu/gv11b/vgpu_fifo_gv11b.o \
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common/linux/vgpu/gv11b/vgpu_subctx_gv11b.o \
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common/linux/vgpu/gv11b/vgpu_tsg_gv11b.o
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nvgpu-$(CONFIG_NVGPU_SUPPORT_CDE) += \
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common/linux/cde.o \
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common/linux/cde_gm20b.o \
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common/linux/cde_gp10b.o
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ifeq ($(CONFIG_DEBUG_FS),y)
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nvgpu-$(CONFIG_NVGPU_SUPPORT_CDE) += \
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common/linux/debug_cde.o
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endif
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@@ -44,6 +44,8 @@
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#include "os_linux.h"
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#include "dmabuf.h"
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#include "channel.h"
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#include "cde_gm20b.h"
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#include "cde_gp10b.h"
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#include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h>
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#include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
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@@ -1749,3 +1751,24 @@ int gk20a_mark_compressible_write(struct gk20a *g, u32 buffer_fd,
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dma_buf_put(dmabuf);
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return 0;
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}
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int nvgpu_cde_init_ops(struct nvgpu_os_linux *l)
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{
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struct gk20a *g = &l->g;
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u32 ver = g->params.gpu_arch + g->params.gpu_impl;
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switch (ver) {
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case GK20A_GPUID_GM20B:
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case GK20A_GPUID_GM20B_B:
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l->ops.cde = gm20b_cde_ops.cde;
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break;
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case NVGPU_GPUID_GP10B:
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l->ops.cde = gp10b_cde_ops.cde;
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break;
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default:
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/* CDE is optional, so today ignoring unknown chip is fine */
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break;
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}
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return 0;
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}
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@@ -321,5 +321,6 @@ int gk20a_prepare_compressible_read(
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int gk20a_mark_compressible_write(
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struct gk20a *g, u32 buffer_fd, u32 valid_compbits, u64 offset,
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u32 zbc_color);
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int nvgpu_cde_init_ops(struct nvgpu_os_linux *l);
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#endif
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@@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2017 NVIDIA Corporation. All rights reserved.
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* Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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@@ -377,7 +377,9 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink)
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gr_gk20a_debugfs_init(g);
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gk20a_pmu_debugfs_init(g);
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gk20a_railgating_debugfs_init(g);
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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gk20a_cde_debugfs_init(g);
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#endif
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gk20a_ce_debugfs_init(g);
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nvgpu_alloc_debugfs_init(g);
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nvgpu_hal_debugfs_init(g);
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@@ -148,7 +148,9 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
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g->aggressive_sync_destroy = platform->aggressive_sync_destroy;
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g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh;
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g->has_syncpoints = platform->has_syncpoints;
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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g->has_cde = platform->has_cde;
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#endif
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g->ptimer_src_freq = platform->ptimer_src_freq;
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g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g));
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g->can_railgate = platform->can_railgate_init;
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@@ -333,10 +333,12 @@ static int gk20a_ctrl_prepare_compressible_read(
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struct gk20a *g,
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struct nvgpu_gpu_prepare_compressible_read_args *args)
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{
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int ret = -ENOSYS;
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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struct nvgpu_fence fence;
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struct gk20a_fence *fence_out = NULL;
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int ret = 0;
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int flags = args->submit_flags;
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fence.id = args->fence.syncpt_id;
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@@ -377,18 +379,21 @@ static int gk20a_ctrl_prepare_compressible_read(
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}
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}
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gk20a_fence_put(fence_out);
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#endif
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return 0;
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return ret;
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}
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static int gk20a_ctrl_mark_compressible_write(
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struct gk20a *g,
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struct nvgpu_gpu_mark_compressible_write_args *args)
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{
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int ret;
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int ret = -ENOSYS;
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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ret = gk20a_mark_compressible_write(g, args->handle,
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args->valid_compbits, args->offset, args->zbc_color);
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#endif
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return ret;
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}
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@@ -48,17 +48,18 @@
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#include "module.h"
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#include "module_usermode.h"
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#include "intr.h"
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#include "cde.h"
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#include "ioctl.h"
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#include "sim.h"
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#include "os_linux.h"
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#include "cde_gm20b.h"
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#include "cde_gp10b.h"
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#include "ctxsw_trace.h"
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#include "driver_common.h"
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#include "channel.h"
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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#include "cde.h"
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#endif
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#define CLASS_NAME "nvidia-gpu"
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/* TODO: Change to e.g. "nvidia-gpu%s" once we have symlinks in place. */
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@@ -180,23 +181,13 @@ static int gk20a_restore_registers(struct gk20a *g)
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static int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
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{
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struct gk20a *g = &l->g;
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u32 ver = g->params.gpu_arch + g->params.gpu_impl;
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int err = 0;
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switch (ver) {
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case GK20A_GPUID_GM20B:
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case GK20A_GPUID_GM20B_B:
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l->ops.cde = gm20b_cde_ops.cde;
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break;
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case NVGPU_GPUID_GP10B:
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l->ops.cde = gp10b_cde_ops.cde;
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break;
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default:
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/* CDE is optional, so today ignoring unknown chip is fine */
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break;
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}
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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err = nvgpu_cde_init_ops(l);
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#endif
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return 0;
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return err;
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}
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int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l)
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@@ -285,8 +276,10 @@ int gk20a_pm_finalize_poweron(struct device *dev)
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gk20a_scale_resume(dev_from_gk20a(g));
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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if (platform->has_cde)
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gk20a_init_cde_support(l);
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#endif
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err = gk20a_sched_ctrl_init(g);
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if (err) {
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@@ -325,7 +318,9 @@ static int gk20a_lockout_registers(struct gk20a *g)
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static int gk20a_pm_prepare_poweroff(struct device *dev)
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{
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struct gk20a *g = get_gk20a(dev);
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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#endif
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int ret = 0;
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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bool irqs_enabled;
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@@ -348,7 +343,9 @@ static int gk20a_pm_prepare_poweroff(struct device *dev)
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gk20a_scale_suspend(dev);
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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gk20a_cde_suspend(l);
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#endif
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ret = gk20a_prepare_poweroff(g);
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if (ret)
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@@ -1239,7 +1236,9 @@ return_err:
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int nvgpu_remove(struct device *dev, struct class *class)
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{
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struct gk20a *g = get_gk20a(dev);
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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#endif
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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int err;
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@@ -1251,8 +1250,10 @@ int nvgpu_remove(struct device *dev, struct class *class)
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if (nvgpu_mem_is_valid(&g->syncpt_mem))
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nvgpu_dma_free(g, &g->syncpt_mem);
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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if (platform->has_cde)
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gk20a_cde_destroy(l);
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#endif
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#ifdef CONFIG_GK20A_CTXSW_TRACE
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gk20a_ctxsw_trace_cleanup(g);
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@@ -217,7 +217,9 @@ struct gk20a_platform {
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/* source frequency for ptimer in hz */
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u32 ptimer_src_freq;
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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bool has_cde;
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#endif
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/* soc name for finding firmware files */
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const char *soc_name;
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@@ -948,7 +948,9 @@ struct gk20a_platform gm20b_tegra_platform = {
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.dump_platform_dependencies = gk20a_tegra_debug_dump,
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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.has_cde = true,
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#endif
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.soc_name = "tegra21x",
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@@ -409,7 +409,9 @@ struct gk20a_platform gp10b_tegra_platform = {
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.dump_platform_dependencies = gk20a_tegra_debug_dump,
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#ifdef CONFIG_NVGPU_SUPPORT_CDE
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.has_cde = true,
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#endif
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.clk_round_rate = gp10b_round_clk_rate,
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.get_clk_freqs = gp10b_clk_get_freqs,
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@@ -211,9 +211,6 @@ static int gv11b_tegra_suspend(struct device *dev)
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struct gk20a_platform gv11b_tegra_platform = {
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.has_syncpoints = true,
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/* no cde. use sysmem compression */
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.has_cde = false,
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/* ptimer src frequency in hz*/
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.ptimer_src_freq = 31250000,
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