diff --git a/drivers/gpu/nvgpu/common/fifo/engines.c b/drivers/gpu/nvgpu/common/fifo/engines.c index a79aa38bc..268848793 100644 --- a/drivers/gpu/nvgpu/common/fifo/engines.c +++ b/drivers/gpu/nvgpu/common/fifo/engines.c @@ -75,7 +75,7 @@ struct nvgpu_engine_info *nvgpu_engine_get_active_eng_info( struct gk20a *g, u32 engine_id) { struct nvgpu_fifo *f = NULL; - u32 engine_id_idx; + u32 i; struct nvgpu_engine_info *info = NULL; if (g == NULL) { @@ -85,10 +85,8 @@ struct nvgpu_engine_info *nvgpu_engine_get_active_eng_info( f = &g->fifo; if (engine_id < f->max_engines) { - for (engine_id_idx = 0; engine_id_idx < f->num_engines; - ++engine_id_idx) { - if (engine_id == - f->active_engines_list[engine_id_idx]) { + for (i = 0U; i < f->num_engines; i++) { + if (engine_id == f->active_engines_list[i]) { info = &f->engine_info[engine_id]; break; } @@ -109,7 +107,7 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, { struct nvgpu_fifo *f = NULL; u32 instance_cnt = 0; - u32 engine_id_idx; + u32 i; u32 active_engine_id = 0; struct nvgpu_engine_info *info = NULL; @@ -119,9 +117,8 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, } f = &g->fifo; - for (engine_id_idx = 0; engine_id_idx < f->num_engines; - ++engine_id_idx) { - active_engine_id = f->active_engines_list[engine_id_idx]; + for (i = 0U; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; info = &f->engine_info[active_engine_id]; if (info->engine_enum == engine_enum) { @@ -140,7 +137,7 @@ u32 nvgpu_engine_get_ids(struct gk20a *g, bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id) { struct nvgpu_fifo *f = NULL; - u32 engine_id_idx; + u32 i; bool valid = false; if (g == NULL) { @@ -150,9 +147,8 @@ bool nvgpu_engine_check_valid_id(struct gk20a *g, u32 engine_id) f = &g->fifo; if (engine_id < f->max_engines) { - for (engine_id_idx = 0; engine_id_idx < f->num_engines; - ++engine_id_idx) { - if (engine_id == f->active_engines_list[engine_id_idx]) { + for (i = 0U; i < f->num_engines; i++) { + if (engine_id == f->active_engines_list[i]) { valid = true; break; } @@ -252,7 +248,7 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) u32 reset_mask = 0; enum nvgpu_fifo_engine engine_enum; struct nvgpu_fifo *f = NULL; - u32 engine_id_idx; + u32 i; struct nvgpu_engine_info *engine_info; u32 active_engine_id = 0; @@ -262,9 +258,8 @@ u32 nvgpu_engine_get_all_ce_reset_mask(struct gk20a *g) f = &g->fifo; - for (engine_id_idx = 0; engine_id_idx < f->num_engines; - ++engine_id_idx) { - active_engine_id = f->active_engines_list[engine_id_idx]; + for (i = 0U; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; engine_info = &f->engine_info[active_engine_id]; engine_enum = engine_info->engine_enum; @@ -640,7 +635,7 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g) u32 ce_runlist_id = nvgpu_engine_get_gr_runlist_id(g); enum nvgpu_fifo_engine engine_enum; struct nvgpu_fifo *f = NULL; - u32 engine_id_idx; + u32 i; struct nvgpu_engine_info *engine_info; u32 active_engine_id = 0U; @@ -650,9 +645,8 @@ u32 nvgpu_engine_get_fast_ce_runlist_id(struct gk20a *g) f = &g->fifo; - for (engine_id_idx = 0U; engine_id_idx < f->num_engines; - ++engine_id_idx) { - active_engine_id = f->active_engines_list[engine_id_idx]; + for (i = 0U; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; engine_info = &f->engine_info[active_engine_id]; engine_enum = engine_info->engine_enum; @@ -699,7 +693,7 @@ end: bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id) { struct nvgpu_fifo *f = NULL; - u32 engine_id_idx; + u32 i; u32 active_engine_id; struct nvgpu_engine_info *engine_info; @@ -709,9 +703,8 @@ bool nvgpu_engine_is_valid_runlist_id(struct gk20a *g, u32 runlist_id) f = &g->fifo; - for (engine_id_idx = 0; engine_id_idx < f->num_engines; - ++engine_id_idx) { - active_engine_id = f->active_engines_list[engine_id_idx]; + for (i = 0U; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; engine_info = nvgpu_engine_get_active_eng_info(g, active_engine_id); if ((engine_info != NULL) && @@ -744,13 +737,13 @@ u32 nvgpu_engine_id_to_mmu_fault_id(struct gk20a *g, u32 engine_id) u32 nvgpu_engine_mmu_fault_id_to_engine_id(struct gk20a *g, u32 fault_id) { - u32 engine_id; + u32 i; u32 active_engine_id; struct nvgpu_engine_info *engine_info; struct nvgpu_fifo *f = &g->fifo; - for (engine_id = 0; engine_id < f->num_engines; engine_id++) { - active_engine_id = f->active_engines_list[engine_id]; + for (i = 0U; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; engine_info = &g->fifo.engine_info[active_engine_id]; if (engine_info->fault_id == fault_id) { @@ -887,17 +880,17 @@ void nvgpu_engine_get_id_and_type(struct gk20a *g, u32 engine_id, u32 nvgpu_engine_find_busy_doing_ctxsw(struct gk20a *g, u32 *id_ptr, bool *is_tsg_ptr) { - u32 engine_id; + u32 i; u32 id = U32_MAX; bool is_tsg = false; u32 mailbox2; u32 act_eng_id = NVGPU_INVALID_ENG_ID; struct nvgpu_engine_status_info engine_status; - for (engine_id = 0U; engine_id < g->fifo.num_engines; engine_id++) { + for (i = 0U; i < g->fifo.num_engines; i++) { bool failing_engine; - act_eng_id = g->fifo.active_engines_list[engine_id]; + act_eng_id = g->fifo.active_engines_list[i]; g->ops.engine_status.read_engine_status_info(g, act_eng_id, &engine_status); @@ -1030,13 +1023,14 @@ u32 nvgpu_engine_mmu_fault_id_to_veid(struct gk20a *g, u32 mmu_fault_id, u32 nvgpu_engine_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, u32 mmu_fault_id, u32 *veid) { - u32 engine_id; + u32 i; u32 act_eng_id = INVAL_ID; struct nvgpu_engine_info *engine_info; struct nvgpu_fifo *f = &g->fifo; - for (engine_id = 0U; engine_id < f->num_engines; engine_id++) { - act_eng_id = f->active_engines_list[engine_id]; + + for (i = 0U; i < f->num_engines; i++) { + act_eng_id = f->active_engines_list[i]; engine_info = &g->fifo.engine_info[act_eng_id]; if (engine_info->engine_enum == NVGPU_ENGINE_GR) { diff --git a/drivers/gpu/nvgpu/common/fifo/runlist.c b/drivers/gpu/nvgpu/common/fifo/runlist.c index 1fc79a2d6..1e8a5c9c4 100644 --- a/drivers/gpu/nvgpu/common/fifo/runlist.c +++ b/drivers/gpu/nvgpu/common/fifo/runlist.c @@ -683,7 +683,7 @@ static void nvgpu_init_runlist_enginfo(struct gk20a *g, struct nvgpu_fifo *f) { struct nvgpu_runlist_info *runlist; struct nvgpu_engine_info *engine_info; - u32 i, active_engine_id, pbdma_id, engine_id; + u32 i, active_engine_id, pbdma_id, j; nvgpu_log_fn(g, " "); @@ -703,8 +703,8 @@ static void nvgpu_init_runlist_enginfo(struct gk20a *g, struct nvgpu_fifo *f) nvgpu_log(g, gpu_dbg_info, "runlist %d : pbdma bitmask 0x%x", runlist->runlist_id, runlist->pbdma_bitmask); - for (engine_id = 0; engine_id < f->num_engines; ++engine_id) { - active_engine_id = f->active_engines_list[engine_id]; + for (j = 0; j < f->num_engines; j++) { + active_engine_id = f->active_engines_list[j]; engine_info = &f->engine_info[active_engine_id]; if (engine_info->runlist_id == runlist->runlist_id) { diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c index 4c1eafff6..fa46d0245 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b.c @@ -40,7 +40,7 @@ void gm20b_mc_isr_stall(struct gk20a *g) { u32 mc_intr_0; - u32 eng_id; + u32 i; u32 act_eng_id = 0U; enum nvgpu_fifo_engine engine_enum; @@ -48,8 +48,8 @@ void gm20b_mc_isr_stall(struct gk20a *g) nvgpu_log(g, gpu_dbg_intr, "stall intr %08x", mc_intr_0); - for (eng_id = 0U; eng_id < g->fifo.num_engines; eng_id++) { - act_eng_id = g->fifo.active_engines_list[eng_id]; + for (i = 0U; i < g->fifo.num_engines; i++) { + act_eng_id = g->fifo.active_engines_list[i]; if ((mc_intr_0 & g->fifo.engine_info[act_eng_id].intr_mask) == 0U) { diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c index b5c4e2a22..3339b6791 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c @@ -65,7 +65,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) { u32 ops = 0U; u32 mc_intr_1; - u32 eng_id; + u32 i; u32 act_eng_id = 0U; enum nvgpu_fifo_engine engine_enum; @@ -75,10 +75,10 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g) ops |= g->ops.fifo.intr_1_isr(g); } - for (eng_id = 0U; eng_id < g->fifo.num_engines; eng_id++) { + for (i = 0U; i < g->fifo.num_engines; i++) { struct nvgpu_engine_info *engine_info; - act_eng_id = g->fifo.active_engines_list[eng_id]; + act_eng_id = g->fifo.active_engines_list[i]; engine_info = &g->fifo.engine_info[act_eng_id]; if ((mc_intr_1 & engine_info->intr_mask) != 0U) { diff --git a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c index 70bb6eb61..b57e33f91 100644 --- a/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c +++ b/drivers/gpu/nvgpu/hal/mc/mc_gp10b_fusa.c @@ -182,7 +182,7 @@ void mc_gp10b_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable) void mc_gp10b_isr_stall(struct gk20a *g) { u32 mc_intr_0; - u32 eng_id; + u32 i; u32 act_eng_id = 0U; enum nvgpu_fifo_engine engine_enum; @@ -190,8 +190,8 @@ void mc_gp10b_isr_stall(struct gk20a *g) nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x", mc_intr_0); - for (eng_id = 0U; eng_id < g->fifo.num_engines; eng_id++) { - act_eng_id = g->fifo.active_engines_list[eng_id]; + for (i = 0U; i < g->fifo.num_engines; i++) { + act_eng_id = g->fifo.active_engines_list[i]; if ((mc_intr_0 & g->fifo.engine_info[act_eng_id].intr_mask) == 0U) { diff --git a/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c b/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c index 9949b3433..e51dbcaa5 100644 --- a/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c +++ b/drivers/gpu/nvgpu/hal/therm/therm_gv11b_fusa.c @@ -141,7 +141,7 @@ void gv11b_therm_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) int gv11b_elcg_init_idle_filters(struct gk20a *g) { u32 gate_ctrl, idle_filter; - u32 engine_id; + u32 i; u32 active_engine_id = 0; struct nvgpu_fifo *f = &g->fifo; @@ -151,8 +151,8 @@ int gv11b_elcg_init_idle_filters(struct gk20a *g) nvgpu_log_info(g, "init clock/power gate reg"); - for (engine_id = 0; engine_id < f->num_engines; engine_id++) { - active_engine_id = f->active_engines_list[engine_id]; + for (i = 0; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; gate_ctrl = nvgpu_readl(g, therm_gate_ctrl_r(active_engine_id)); gate_ctrl = set_field(gate_ctrl, diff --git a/userspace/units/cg/nvgpu-cg.c b/userspace/units/cg/nvgpu-cg.c index b9cce6b39..932644de1 100644 --- a/userspace/units/cg/nvgpu-cg.c +++ b/userspace/units/cg/nvgpu-cg.c @@ -521,12 +521,12 @@ int test_cg(struct unit_module *m, struct gk20a *g, void *args) static int elcg_add_engine_therm_regs(struct gk20a *g) { - u32 engine_idx; + u32 i; u32 active_engine_id = 0; struct nvgpu_fifo *f = &g->fifo; - for (engine_idx = 0; engine_idx < f->num_engines; ++engine_idx) { - active_engine_id = f->active_engines_list[engine_idx]; + for (i = 0U; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; if (nvgpu_posix_io_add_reg_space(g, therm_gate_ctrl_r(active_engine_id), 0x4) != 0) { @@ -539,12 +539,12 @@ static int elcg_add_engine_therm_regs(struct gk20a *g) static void elcg_delete_engine_therm_regs(struct gk20a *g) { - u32 engine_idx; + u32 i; u32 active_engine_id = 0; struct nvgpu_fifo *f = &g->fifo; - for (engine_idx = 0; engine_idx < f->num_engines; ++engine_idx) { - active_engine_id = f->active_engines_list[engine_idx]; + for (i = 0U; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; nvgpu_posix_io_delete_reg_space(g, therm_gate_ctrl_r(active_engine_id)); @@ -553,14 +553,14 @@ static void elcg_delete_engine_therm_regs(struct gk20a *g) static int verify_elcg_status(struct gk20a *g, u32 cg_mode) { - u32 engine_idx; + u32 i; u32 active_engine_id = 0; struct nvgpu_fifo *f = &g->fifo; int err = UNIT_SUCCESS; u32 gate_r; - for (engine_idx = 0; engine_idx < f->num_engines; ++engine_idx) { - active_engine_id = f->active_engines_list[engine_idx]; + for (i = 0; i < f->num_engines; i++) { + active_engine_id = f->active_engines_list[i]; gate_r = nvgpu_readl(g, therm_gate_ctrl_r(active_engine_id)); if (cg_mode == ELCG_RUN) {